Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(396)

Side by Side Diff: src/arm64/simulator-arm64.h

Issue 213943002: Change arm64 simulator register backing store. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 9 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch | Annotate | Revision Log
« no previous file with comments | « no previous file | no next file » | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 141 matching lines...) Expand 10 before | Expand all | Expand 10 after
152 // describes the bits which are not modifiable. 152 // describes the bits which are not modifiable.
153 SimSystemRegister(uint32_t value, uint32_t write_ignore_mask) 153 SimSystemRegister(uint32_t value, uint32_t write_ignore_mask)
154 : value_(value), write_ignore_mask_(write_ignore_mask) { } 154 : value_(value), write_ignore_mask_(write_ignore_mask) { }
155 155
156 uint32_t value_; 156 uint32_t value_;
157 uint32_t write_ignore_mask_; 157 uint32_t write_ignore_mask_;
158 }; 158 };
159 159
160 160
161 // Represent a register (r0-r31, v0-v31). 161 // Represent a register (r0-r31, v0-v31).
162 template<int kSizeInBytes>
163 class SimRegisterBase { 162 class SimRegisterBase {
164 public: 163 public:
165 template<typename T> 164 void Set(int64_t new_value, unsigned size) {
166 void Set(T new_value, unsigned size = sizeof(T)) { 165 ASSERT(size/8 <= kXRegSize);
jbramley 2014/03/27 17:50:42 There are actually only two supported sizes at the
Fritz 2014/03/27 19:58:33 Is there a plan to use Q registers? I think this
167 ASSERT(size <= kSizeInBytes);
168 ASSERT(size <= sizeof(new_value));
169 // All AArch64 registers are zero-extending; Writing a W register clears the 166 // All AArch64 registers are zero-extending; Writing a W register clears the
170 // top bits of the corresponding X register. 167 // top bits of the corresponding X register.
171 memset(value_, 0, kSizeInBytes); 168 value_ = new_value;
172 memcpy(value_, &new_value, size); 169 if (size == kSRegSizeInBits) {
jbramley 2014/03/27 17:50:42 Why kSRegSize here? These can be any register type
Fritz 2014/03/27 19:58:33 I choose kSRegSize because I was following the log
170 value_ &= kSRegMask;
171 }
172 }
173
174 template<typename T>
175 void Set(T new_value) {
176 union SetUnion {
177 T new_value;
178 int64_t value;
179 } reg = { new_value };
jbramley 2014/03/27 17:50:42 This isn't safe for type-aliasing rules. In anothe
Fritz 2014/03/27 19:58:33 I tried this method earlier. https://codereview.ch
Sven Panne 2014/03/28 11:46:04 I don't think that such a thing is possible: IIRC,
jbramley 2014/03/28 11:59:58 It seems to be allowed in C99 TC3 (dated the Septe
180 STATIC_ASSERT(sizeof(union SetUnion) == sizeof(value_));
jbramley 2014/03/27 17:50:42 That assertion isn't sufficient; if T is smaller t
Fritz 2014/03/27 19:58:33 Which is what I want. From a conceptual standpoin
181
182 value_ = reg.value;
jbramley 2014/03/27 17:50:42 Again, if T is smaller than value_, this won't cor
173 } 183 }
174 184
175 // Copy 'size' bytes of the register to the result, and zero-extend to fill 185 // Copy 'size' bytes of the register to the result, and zero-extend to fill
176 // the result. 186 // the result.
177 template<typename T> 187 int64_t Get(unsigned size) const {
178 T Get(unsigned size = sizeof(T)) const { 188 ASSERT(size/8 <= kXRegSize);
179 ASSERT(size <= kSizeInBytes); 189 int64_t result = value_;
180 T result; 190 if (size == kSRegSizeInBits) {
181 memset(&result, 0, sizeof(result)); 191 result &= kSRegMask;
182 memcpy(&result, value_, size); 192 }
183 return result; 193 return result;
184 } 194 }
185 195
196 template<typename T>
197 T Get() const {
198 union GetUnion {
199 int64_t value;
200 T result;
201 } reg = { value_ };
202 STATIC_ASSERT(sizeof(union GetUnion) == sizeof(value_));
203
204 return reg.result;
205 }
206
186 protected: 207 protected:
187 uint8_t value_[kSizeInBytes]; 208 int64_t value_;
188 }; 209 };
189 typedef SimRegisterBase<kXRegSize> SimRegister; // r0-r31 210
190 typedef SimRegisterBase<kDRegSize> SimFPRegister; // v0-v31 211 STATIC_ASSERT(kXRegSize == kDRegSize);
212 typedef SimRegisterBase SimRegister; // r0-r31
213 typedef SimRegisterBase SimFPRegister; // v0-v31
191 214
192 215
193 class Simulator : public DecoderVisitor { 216 class Simulator : public DecoderVisitor {
194 public: 217 public:
195 explicit Simulator(Decoder<DispatchingDecoderVisitor>* decoder, 218 explicit Simulator(Decoder<DispatchingDecoderVisitor>* decoder,
196 Isolate* isolate = NULL, 219 Isolate* isolate = NULL,
197 FILE* stream = stderr); 220 FILE* stream = stderr);
198 Simulator(); 221 Simulator();
199 ~Simulator(); 222 ~Simulator();
200 223
(...skipping 146 matching lines...) Expand 10 before | Expand all | Expand 10 after
347 LogProcessorState(); 370 LogProcessorState();
348 increment_pc(); 371 increment_pc();
349 CheckBreakpoints(); 372 CheckBreakpoints();
350 } 373 }
351 374
352 // Declare all Visitor functions. 375 // Declare all Visitor functions.
353 #define DECLARE(A) void Visit##A(Instruction* instr); 376 #define DECLARE(A) void Visit##A(Instruction* instr);
354 VISITOR_LIST(DECLARE) 377 VISITOR_LIST(DECLARE)
355 #undef DECLARE 378 #undef DECLARE
356 379
380 bool Reg31ZeroMode(unsigned code, Reg31Mode r31mode) const {
381 return ((code == 31) && (r31mode == Reg31IsZeroRegister));
382 }
383
357 // Register accessors. 384 // Register accessors.
358
359 // Return 'size' bits of the value of an integer register, as the specified 385 // Return 'size' bits of the value of an integer register, as the specified
360 // type. The value is zero-extended to fill the result. 386 // type. The value is zero-extended to fill the result.
361 // 387 //
362 // The only supported values of 'size' are kXRegSizeInBits and 388 // The only supported values of 'size' are kXRegSizeInBits and
363 // kWRegSizeInBits. 389 // kWRegSizeInBits.
364 template<typename T> 390 int64_t reg(unsigned size, unsigned code,
365 T reg(unsigned size, unsigned code,
366 Reg31Mode r31mode = Reg31IsZeroRegister) const { 391 Reg31Mode r31mode = Reg31IsZeroRegister) const {
367 unsigned size_in_bytes = size / 8;
368 ASSERT(size_in_bytes <= sizeof(T));
369 ASSERT((size == kXRegSizeInBits) || (size == kWRegSizeInBits)); 392 ASSERT((size == kXRegSizeInBits) || (size == kWRegSizeInBits));
370 ASSERT(code < kNumberOfRegisters); 393 ASSERT(code < kNumberOfRegisters);
371 394
372 if ((code == 31) && (r31mode == Reg31IsZeroRegister)) { 395 if (Reg31ZeroMode(code, r31mode)) {
373 T result; 396 return 0;
374 memset(&result, 0, sizeof(result));
375 return result;
376 } 397 }
377 return registers_[code].Get<T>(size_in_bytes); 398 return registers_[code].Get(size);
378 } 399 }
379 400
380 // Like reg(), but infer the access size from the template type. 401 // Like reg(), but infer the access size from the template type.
381 template<typename T> 402 template<typename T>
382 T reg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const { 403 T reg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
383 return reg<T>(sizeof(T) * 8, code, r31mode); 404 ASSERT(code < kNumberOfRegisters);
405 if (Reg31ZeroMode(code, r31mode)) {
406 return 0;
407 }
408 return registers_[code].Get<T>();
384 } 409 }
385 410
386 // Common specialized accessors for the reg() template. 411 // Common specialized accessors for the reg() template.
387 int32_t wreg(unsigned code, 412 int32_t wreg(unsigned code,
388 Reg31Mode r31mode = Reg31IsZeroRegister) const { 413 Reg31Mode r31mode = Reg31IsZeroRegister) const {
389 return reg<int32_t>(code, r31mode); 414 return reg<int32_t>(code, r31mode);
390 } 415 }
391 416
392 int64_t xreg(unsigned code, 417 int64_t xreg(unsigned code,
393 Reg31Mode r31mode = Reg31IsZeroRegister) const { 418 Reg31Mode r31mode = Reg31IsZeroRegister) const {
394 return reg<int64_t>(code, r31mode); 419 return reg<int64_t>(code, r31mode);
395 } 420 }
396 421
397 int64_t reg(unsigned size, unsigned code,
398 Reg31Mode r31mode = Reg31IsZeroRegister) const {
399 return reg<int64_t>(size, code, r31mode);
400 }
401
402 // Write 'size' bits of 'value' into an integer register. The value is 422 // Write 'size' bits of 'value' into an integer register. The value is
403 // zero-extended. This behaviour matches AArch64 register writes. 423 // zero-extended. This behaviour matches AArch64 register writes.
404 // 424 //
405 // The only supported values of 'size' are kXRegSizeInBits and 425 // The only supported values of 'size' are kXRegSizeInBits and
406 // kWRegSizeInBits. 426 // kWRegSizeInBits.
407 template<typename T> 427 template<typename T>
408 void set_reg(unsigned size, unsigned code, T value, 428 void set_reg(unsigned size, unsigned code, T value,
409 Reg31Mode r31mode = Reg31IsZeroRegister) { 429 Reg31Mode r31mode = Reg31IsZeroRegister) {
410 unsigned size_in_bytes = size / 8;
411 ASSERT(size_in_bytes <= sizeof(T));
412 ASSERT((size == kXRegSizeInBits) || (size == kWRegSizeInBits)); 430 ASSERT((size == kXRegSizeInBits) || (size == kWRegSizeInBits));
413 ASSERT(code < kNumberOfRegisters); 431 ASSERT(code < kNumberOfRegisters);
414 432
415 if ((code == 31) && (r31mode == Reg31IsZeroRegister)) { 433 if (!Reg31ZeroMode(code, r31mode))
416 return; 434 registers_[code].Set(value, size);
417 }
418 return registers_[code].Set(value, size_in_bytes);
419 } 435 }
420 436
421 // Like set_reg(), but infer the access size from the template type. 437 // Like set_reg(), but infer the access size from the template type.
422 template<typename T> 438 template<typename T>
423 void set_reg(unsigned code, T value, 439 void set_reg(unsigned code, T value,
424 Reg31Mode r31mode = Reg31IsZeroRegister) { 440 Reg31Mode r31mode = Reg31IsZeroRegister) {
425 set_reg(sizeof(value) * 8, code, value, r31mode); 441 ASSERT(code < kNumberOfRegisters);
442 if (!Reg31ZeroMode(code, r31mode))
443 registers_[code].Set(value);
426 } 444 }
427 445
428 // Common specialized accessors for the set_reg() template. 446 // Common specialized accessors for the set_reg() template.
429 void set_wreg(unsigned code, int32_t value, 447 void set_wreg(unsigned code, int32_t value,
430 Reg31Mode r31mode = Reg31IsZeroRegister) { 448 Reg31Mode r31mode = Reg31IsZeroRegister) {
431 set_reg(kWRegSizeInBits, code, value, r31mode); 449 set_reg(code, value, r31mode);
432 } 450 }
433 451
434 void set_xreg(unsigned code, int64_t value, 452 void set_xreg(unsigned code, int64_t value,
435 Reg31Mode r31mode = Reg31IsZeroRegister) { 453 Reg31Mode r31mode = Reg31IsZeroRegister) {
436 set_reg(kXRegSizeInBits, code, value, r31mode); 454 set_reg(code, value, r31mode);
437 } 455 }
438 456
439 // Commonly-used special cases. 457 // Commonly-used special cases.
440 template<typename T> 458 template<typename T>
441 void set_lr(T value) { 459 void set_lr(T value) {
442 ASSERT(sizeof(T) == kPointerSize); 460 ASSERT(sizeof(T) == kPointerSize);
443 set_reg(kLinkRegCode, value); 461 set_reg(kLinkRegCode, value);
444 } 462 }
445 463
446 template<typename T> 464 template<typename T>
447 void set_sp(T value) { 465 void set_sp(T value) {
448 ASSERT(sizeof(T) == kPointerSize); 466 ASSERT(sizeof(T) == kPointerSize);
449 set_reg(31, value, Reg31IsStackPointer); 467 set_reg(31, value, Reg31IsStackPointer);
450 } 468 }
451 469
452 int64_t sp() { return xreg(31, Reg31IsStackPointer); } 470 int64_t sp() { return xreg(31, Reg31IsStackPointer); }
453 int64_t jssp() { return xreg(kJSSPCode, Reg31IsStackPointer); } 471 int64_t jssp() { return xreg(kJSSPCode, Reg31IsStackPointer); }
454 int64_t fp() { 472 int64_t fp() {
455 return xreg(kFramePointerRegCode, Reg31IsStackPointer); 473 return xreg(kFramePointerRegCode, Reg31IsStackPointer);
456 } 474 }
457 Instruction* lr() { return reg<Instruction*>(kLinkRegCode); } 475 Instruction* lr() { return reg<Instruction*>(kLinkRegCode); }
458 476
459 Address get_sp() { return reg<Address>(31, Reg31IsStackPointer); } 477 Address get_sp() { return reg<Address>(31, Reg31IsStackPointer); }
460 478
461 // Return 'size' bits of the value of a floating-point register, as the
462 // specified type. The value is zero-extended to fill the result.
463 //
464 // The only supported values of 'size' are kDRegSizeInBits and
465 // kSRegSizeInBits.
466 template<typename T>
467 T fpreg(unsigned size, unsigned code) const {
468 unsigned size_in_bytes = size / 8;
469 ASSERT(size_in_bytes <= sizeof(T));
470 ASSERT((size == kDRegSizeInBits) || (size == kSRegSizeInBits));
471 ASSERT(code < kNumberOfFPRegisters);
472 return fpregisters_[code].Get<T>(size_in_bytes);
473 }
474
475 // Like fpreg(), but infer the access size from the template type.
476 template<typename T> 479 template<typename T>
477 T fpreg(unsigned code) const { 480 T fpreg(unsigned code) const {
478 return fpreg<T>(sizeof(T) * 8, code); 481 ASSERT(code < kNumberOfRegisters);
482 return fpregisters_[code].Get<T>();
479 } 483 }
480 484
481 // Common specialized accessors for the fpreg() template. 485 // Common specialized accessors for the fpreg() template.
482 float sreg(unsigned code) const { 486 float sreg(unsigned code) const {
483 return fpreg<float>(code); 487 return fpreg<float>(code);
484 } 488 }
485 489
486 uint32_t sreg_bits(unsigned code) const { 490 uint32_t sreg_bits(unsigned code) const {
487 return fpreg<uint32_t>(code); 491 return fpreg<uint32_t>(code);
488 } 492 }
(...skipping 15 matching lines...) Expand all
504 return 0.0; 508 return 0.0;
505 } 509 }
506 } 510 }
507 511
508 // Write 'value' into a floating-point register. The value is zero-extended. 512 // Write 'value' into a floating-point register. The value is zero-extended.
509 // This behaviour matches AArch64 register writes. 513 // This behaviour matches AArch64 register writes.
510 template<typename T> 514 template<typename T>
511 void set_fpreg(unsigned code, T value) { 515 void set_fpreg(unsigned code, T value) {
512 ASSERT((sizeof(value) == kDRegSize) || (sizeof(value) == kSRegSize)); 516 ASSERT((sizeof(value) == kDRegSize) || (sizeof(value) == kSRegSize));
513 ASSERT(code < kNumberOfFPRegisters); 517 ASSERT(code < kNumberOfFPRegisters);
514 fpregisters_[code].Set(value, sizeof(value)); 518 fpregisters_[code].Set(value);
515 } 519 }
516 520
517 // Common specialized accessors for the set_fpreg() template. 521 // Common specialized accessors for the set_fpreg() template.
518 void set_sreg(unsigned code, float value) { 522 void set_sreg(unsigned code, float value) {
519 set_fpreg(code, value); 523 set_fpreg(code, value);
520 } 524 }
521 525
522 void set_sreg_bits(unsigned code, uint32_t value) { 526 void set_sreg_bits(unsigned code, uint32_t value) {
523 set_fpreg(code, value); 527 set_fpreg(code, value);
524 } 528 }
(...skipping 374 matching lines...) Expand 10 before | Expand all | Expand 10 after
899 static void UnregisterCTryCatch() { 903 static void UnregisterCTryCatch() {
900 Simulator::current(Isolate::Current())->PopAddress(); 904 Simulator::current(Isolate::Current())->PopAddress();
901 } 905 }
902 }; 906 };
903 907
904 #endif // !defined(USE_SIMULATOR) 908 #endif // !defined(USE_SIMULATOR)
905 909
906 } } // namespace v8::internal 910 } } // namespace v8::internal
907 911
908 #endif // V8_ARM64_SIMULATOR_ARM64_H_ 912 #endif // V8_ARM64_SIMULATOR_ARM64_H_
OLDNEW
« no previous file with comments | « no previous file | no next file » | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698