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1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <stdlib.h> | 5 #include <stdlib.h> |
6 #include <cmath> | 6 #include <cmath> |
7 #include <cstdarg> | 7 #include <cstdarg> |
8 #include "v8.h" | 8 #include "v8.h" |
9 | 9 |
10 #if V8_TARGET_ARCH_ARM64 | 10 #if V8_TARGET_ARCH_ARM64 |
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816 } | 816 } |
817 } | 817 } |
818 if ((strcmp("csp", name) == 0) || (strcmp("wcsp", name) == 0)) { | 818 if ((strcmp("csp", name) == 0) || (strcmp("wcsp", name) == 0)) { |
819 return kSPRegInternalCode; | 819 return kSPRegInternalCode; |
820 } | 820 } |
821 return -1; | 821 return -1; |
822 } | 822 } |
823 | 823 |
824 | 824 |
825 // Helpers --------------------------------------------------------------------- | 825 // Helpers --------------------------------------------------------------------- |
826 int64_t Simulator::AddWithCarry(unsigned reg_size, | 826 template <typename T> |
827 bool set_flags, | 827 T Simulator::AddWithCarry(bool set_flags, |
828 int64_t src1, | 828 T src1, |
829 int64_t src2, | 829 T src2, |
830 int64_t carry_in) { | 830 T carry_in) { |
831 typedef typename make_unsigned<T>::type unsignedT; | |
831 ASSERT((carry_in == 0) || (carry_in == 1)); | 832 ASSERT((carry_in == 0) || (carry_in == 1)); |
832 ASSERT((reg_size == kXRegSizeInBits) || (reg_size == kWRegSizeInBits)); | |
833 | 833 |
834 uint64_t u1, u2; | 834 T signed_sum = src1 + src2 + carry_in; |
835 int64_t result; | 835 T result = signed_sum; |
836 int64_t signed_sum = src1 + src2 + carry_in; | |
837 | 836 |
838 bool N, Z, C, V; | 837 bool N, Z, C, V; |
839 | 838 |
840 if (reg_size == kWRegSizeInBits) { | 839 // Compute the C flag |
Fritz
2014/05/27 23:07:03
Using the logic from the arm simulator here. I do
| |
841 u1 = static_cast<uint64_t>(src1) & kWRegMask; | 840 unsignedT u1 = static_cast<unsignedT>(src1); |
842 u2 = static_cast<uint64_t>(src2) & kWRegMask; | 841 unsignedT u2 = static_cast<unsignedT>(src2); |
842 unsignedT urest = std::numeric_limits<unsignedT>::max() - u1; | |
843 C = (u2 > urest) || (carry_in && (((u2 + 1) > urest) || (u2 > (urest - 1)))); | |
843 | 844 |
844 result = signed_sum & kWRegMask; | 845 // Overflow iff the sign bit is the same for the two inputs and different |
845 // Compute the C flag by comparing the sum to the max unsigned integer. | 846 // for the result. |
846 C = ((kWMaxUInt - u1) < (u2 + carry_in)) || | 847 V = ((src1 ^ src2) >= 0) && ((src1 ^ result) < 0); |
847 ((kWMaxUInt - u1 - carry_in) < u2); | |
848 // Overflow iff the sign bit is the same for the two inputs and different | |
849 // for the result. | |
850 int64_t s_src1 = src1 << (kXRegSizeInBits - kWRegSizeInBits); | |
851 int64_t s_src2 = src2 << (kXRegSizeInBits - kWRegSizeInBits); | |
852 int64_t s_result = result << (kXRegSizeInBits - kWRegSizeInBits); | |
853 V = ((s_src1 ^ s_src2) >= 0) && ((s_src1 ^ s_result) < 0); | |
854 | 848 |
855 } else { | 849 N = CalcNFlag(result); |
856 u1 = static_cast<uint64_t>(src1); | |
857 u2 = static_cast<uint64_t>(src2); | |
858 | |
859 result = signed_sum; | |
860 // Compute the C flag by comparing the sum to the max unsigned integer. | |
861 C = ((kXMaxUInt - u1) < (u2 + carry_in)) || | |
862 ((kXMaxUInt - u1 - carry_in) < u2); | |
863 // Overflow iff the sign bit is the same for the two inputs and different | |
864 // for the result. | |
865 V = ((src1 ^ src2) >= 0) && ((src1 ^ result) < 0); | |
866 } | |
867 | |
868 N = CalcNFlag(result, reg_size); | |
869 Z = CalcZFlag(result); | 850 Z = CalcZFlag(result); |
870 | 851 |
871 if (set_flags) { | 852 if (set_flags) { |
872 nzcv().SetN(N); | 853 nzcv().SetN(N); |
873 nzcv().SetZ(Z); | 854 nzcv().SetZ(Z); |
874 nzcv().SetC(C); | 855 nzcv().SetC(C); |
875 nzcv().SetV(V); | 856 nzcv().SetV(V); |
876 } | 857 } |
877 return result; | 858 return result; |
878 } | 859 } |
879 | 860 |
880 | 861 |
881 int64_t Simulator::ShiftOperand(unsigned reg_size, | 862 template<typename T> |
882 int64_t value, | 863 void Simulator::AddSubWithCarry(Instruction* instr) { |
883 Shift shift_type, | 864 T op2 = reg<T>(instr->Rm()); |
884 unsigned amount) { | 865 T new_val; |
866 | |
867 if ((instr->Mask(AddSubOpMask) == SUB) || instr->Mask(AddSubOpMask) == SUBS) { | |
868 op2 = ~op2; | |
869 } | |
870 | |
871 new_val = AddWithCarry<T>(instr->FlagsUpdate(), | |
872 reg<T>(instr->Rn()), | |
873 op2, | |
874 nzcv().C()); | |
875 | |
876 set_reg<T>(instr->Rd(), new_val); | |
877 } | |
878 | |
879 template <typename T> | |
880 T Simulator::ShiftOperand(T value, Shift shift_type, unsigned amount) { | |
881 typedef typename make_unsigned<T>::type unsignedT; | |
882 | |
885 if (amount == 0) { | 883 if (amount == 0) { |
886 return value; | 884 return value; |
887 } | 885 } |
888 int64_t mask = reg_size == kXRegSizeInBits ? kXRegMask : kWRegMask; | 886 |
889 switch (shift_type) { | 887 switch (shift_type) { |
890 case LSL: | 888 case LSL: |
891 return (value << amount) & mask; | 889 return value << amount; |
892 case LSR: | 890 case LSR: |
893 return static_cast<uint64_t>(value) >> amount; | 891 return static_cast<unsignedT>(value) >> amount; |
894 case ASR: { | 892 case ASR: |
895 // Shift used to restore the sign. | 893 return value >> amount; |
896 unsigned s_shift = kXRegSizeInBits - reg_size; | 894 case ROR: |
897 // Value with its sign restored. | 895 return (static_cast<unsignedT>(value) >> amount) | |
898 int64_t s_value = (value << s_shift) >> s_shift; | 896 ((value & ((1L << amount) - 1L)) << |
899 return (s_value >> amount) & mask; | 897 (sizeof(unsignedT) * 8 - amount)); |
900 } | |
901 case ROR: { | |
902 if (reg_size == kWRegSizeInBits) { | |
903 value &= kWRegMask; | |
904 } | |
905 return (static_cast<uint64_t>(value) >> amount) | | |
906 ((value & ((1L << amount) - 1L)) << (reg_size - amount)); | |
907 } | |
908 default: | 898 default: |
909 UNIMPLEMENTED(); | 899 UNIMPLEMENTED(); |
910 return 0; | 900 return 0; |
911 } | 901 } |
912 } | 902 } |
913 | 903 |
914 | 904 |
915 int64_t Simulator::ExtendValue(unsigned reg_size, | 905 template <typename T> |
916 int64_t value, | 906 T Simulator::ExtendValue(T value, Extend extend_type, unsigned left_shift) { |
917 Extend extend_type, | 907 const unsigned kSignExtendBShift = (sizeof(T) - 1) * 8; |
918 unsigned left_shift) { | 908 const unsigned kSignExtendHShift = (sizeof(T) - 2) * 8; |
909 const unsigned kSignExtendWShift = (sizeof(T) - 4) * 8; | |
910 | |
919 switch (extend_type) { | 911 switch (extend_type) { |
920 case UXTB: | 912 case UXTB: |
921 value &= kByteMask; | 913 value &= kByteMask; |
922 break; | 914 break; |
923 case UXTH: | 915 case UXTH: |
924 value &= kHalfWordMask; | 916 value &= kHalfWordMask; |
925 break; | 917 break; |
926 case UXTW: | 918 case UXTW: |
927 value &= kWordMask; | 919 value &= kWordMask; |
928 break; | 920 break; |
929 case SXTB: | 921 case SXTB: |
930 value = (value << 56) >> 56; | 922 value = (value << kSignExtendBShift) >> kSignExtendBShift; |
931 break; | 923 break; |
932 case SXTH: | 924 case SXTH: |
933 value = (value << 48) >> 48; | 925 value = (value << kSignExtendHShift) >> kSignExtendHShift; |
934 break; | 926 break; |
935 case SXTW: | 927 case SXTW: |
936 value = (value << 32) >> 32; | 928 value = (value << kSignExtendWShift) >> kSignExtendWShift; |
937 break; | 929 break; |
938 case UXTX: | 930 case UXTX: |
939 case SXTX: | 931 case SXTX: |
940 break; | 932 break; |
941 default: | 933 default: |
942 UNREACHABLE(); | 934 UNREACHABLE(); |
943 } | 935 } |
944 int64_t mask = (reg_size == kXRegSizeInBits) ? kXRegMask : kWRegMask; | 936 return value << left_shift; |
945 return (value << left_shift) & mask; | |
946 } | 937 } |
947 | 938 |
948 | 939 |
940 template <typename T> | |
941 void Simulator::Extract(Instruction* instr) { | |
942 unsigned lsb = instr->ImmS(); | |
943 T op2 = reg<T>(instr->Rm()); | |
944 T result = op2; | |
945 | |
946 if (lsb) { | |
947 T op1 = reg<T>(instr->Rn()); | |
948 result = op2 >> lsb | (op1 << ((sizeof(T) * 8) - lsb)); | |
949 } | |
950 set_reg<T>(instr->Rd(), result); | |
951 } | |
952 | |
953 | |
949 template<> double Simulator::FPDefaultNaN<double>() const { | 954 template<> double Simulator::FPDefaultNaN<double>() const { |
950 return kFP64DefaultNaN; | 955 return kFP64DefaultNaN; |
951 } | 956 } |
952 | 957 |
953 | 958 |
954 template<> float Simulator::FPDefaultNaN<float>() const { | 959 template<> float Simulator::FPDefaultNaN<float>() const { |
955 return kFP32DefaultNaN; | 960 return kFP32DefaultNaN; |
956 } | 961 } |
957 | 962 |
958 | 963 |
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1249 case CBNZ_w: take_branch = (wreg(rt) != 0); break; | 1254 case CBNZ_w: take_branch = (wreg(rt) != 0); break; |
1250 case CBNZ_x: take_branch = (xreg(rt) != 0); break; | 1255 case CBNZ_x: take_branch = (xreg(rt) != 0); break; |
1251 default: UNIMPLEMENTED(); | 1256 default: UNIMPLEMENTED(); |
1252 } | 1257 } |
1253 if (take_branch) { | 1258 if (take_branch) { |
1254 set_pc(instr->ImmPCOffsetTarget()); | 1259 set_pc(instr->ImmPCOffsetTarget()); |
1255 } | 1260 } |
1256 } | 1261 } |
1257 | 1262 |
1258 | 1263 |
1259 void Simulator::AddSubHelper(Instruction* instr, int64_t op2) { | 1264 template<typename T> |
1260 unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits | 1265 void Simulator::AddSubHelper(Instruction* instr, T op2) { |
1261 : kWRegSizeInBits; | |
1262 bool set_flags = instr->FlagsUpdate(); | 1266 bool set_flags = instr->FlagsUpdate(); |
1263 int64_t new_val = 0; | 1267 T new_val = 0; |
1264 Instr operation = instr->Mask(AddSubOpMask); | 1268 Instr operation = instr->Mask(AddSubOpMask); |
1265 | 1269 |
1266 switch (operation) { | 1270 switch (operation) { |
1267 case ADD: | 1271 case ADD: |
1268 case ADDS: { | 1272 case ADDS: { |
1269 new_val = AddWithCarry(reg_size, | 1273 new_val = AddWithCarry<T>(set_flags, |
1270 set_flags, | 1274 reg<T>(instr->Rn(), instr->RnMode()), |
1271 reg(reg_size, instr->Rn(), instr->RnMode()), | 1275 op2); |
1272 op2); | |
1273 break; | 1276 break; |
1274 } | 1277 } |
1275 case SUB: | 1278 case SUB: |
1276 case SUBS: { | 1279 case SUBS: { |
1277 new_val = AddWithCarry(reg_size, | 1280 new_val = AddWithCarry<T>(set_flags, |
1278 set_flags, | 1281 reg<T>(instr->Rn(), instr->RnMode()), |
1279 reg(reg_size, instr->Rn(), instr->RnMode()), | 1282 ~op2, |
1280 ~op2, | 1283 1); |
1281 1); | |
1282 break; | 1284 break; |
1283 } | 1285 } |
1284 default: UNREACHABLE(); | 1286 default: UNREACHABLE(); |
1285 } | 1287 } |
1286 | 1288 |
1287 set_reg(reg_size, instr->Rd(), new_val, instr->RdMode()); | 1289 set_reg<T>(instr->Rd(), new_val, instr->RdMode()); |
1288 } | 1290 } |
1289 | 1291 |
1290 | 1292 |
1291 void Simulator::VisitAddSubShifted(Instruction* instr) { | 1293 void Simulator::VisitAddSubShifted(Instruction* instr) { |
1292 unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits | 1294 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); |
1293 : kWRegSizeInBits; | 1295 unsigned shift_amount = instr->ImmDPShift(); |
1294 int64_t op2 = ShiftOperand(reg_size, | 1296 |
1295 reg(reg_size, instr->Rm()), | 1297 if (instr->SixtyFourBits()) { |
1296 static_cast<Shift>(instr->ShiftDP()), | 1298 int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); |
1297 instr->ImmDPShift()); | 1299 AddSubHelper(instr, op2); |
1298 AddSubHelper(instr, op2); | 1300 } else { |
1301 int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); | |
1302 AddSubHelper(instr, op2); | |
1303 } | |
1299 } | 1304 } |
1300 | 1305 |
1301 | 1306 |
1302 void Simulator::VisitAddSubImmediate(Instruction* instr) { | 1307 void Simulator::VisitAddSubImmediate(Instruction* instr) { |
1303 int64_t op2 = instr->ImmAddSub() << ((instr->ShiftAddSub() == 1) ? 12 : 0); | 1308 int64_t op2 = instr->ImmAddSub() << ((instr->ShiftAddSub() == 1) ? 12 : 0); |
1304 AddSubHelper(instr, op2); | 1309 if (instr->SixtyFourBits()) { |
1310 AddSubHelper<int64_t>(instr, op2); | |
1311 } else { | |
1312 AddSubHelper<int32_t>(instr, op2); | |
1313 } | |
1305 } | 1314 } |
1306 | 1315 |
1307 | 1316 |
1308 void Simulator::VisitAddSubExtended(Instruction* instr) { | 1317 void Simulator::VisitAddSubExtended(Instruction* instr) { |
1309 unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits | 1318 Extend ext = static_cast<Extend>(instr->ExtendMode()); |
1310 : kWRegSizeInBits; | 1319 unsigned left_shift = instr->ImmExtendShift(); |
1311 int64_t op2 = ExtendValue(reg_size, | 1320 if (instr->SixtyFourBits()) { |
1312 reg(reg_size, instr->Rm()), | 1321 int64_t op2 = ExtendValue(xreg(instr->Rm()), ext, left_shift); |
1313 static_cast<Extend>(instr->ExtendMode()), | 1322 AddSubHelper(instr, op2); |
1314 instr->ImmExtendShift()); | 1323 } else { |
1315 AddSubHelper(instr, op2); | 1324 int32_t op2 = ExtendValue(wreg(instr->Rm()), ext, left_shift); |
1325 AddSubHelper(instr, op2); | |
1326 } | |
1316 } | 1327 } |
1317 | 1328 |
1318 | 1329 |
1319 void Simulator::VisitAddSubWithCarry(Instruction* instr) { | 1330 void Simulator::VisitAddSubWithCarry(Instruction* instr) { |
1320 unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits | 1331 if (instr->SixtyFourBits()) { |
1321 : kWRegSizeInBits; | 1332 AddSubWithCarry<int64_t>(instr); |
1322 int64_t op2 = reg(reg_size, instr->Rm()); | 1333 } else { |
1323 int64_t new_val; | 1334 AddSubWithCarry<int32_t>(instr); |
1324 | |
1325 if ((instr->Mask(AddSubOpMask) == SUB) || instr->Mask(AddSubOpMask) == SUBS) { | |
1326 op2 = ~op2; | |
1327 } | 1335 } |
1328 | |
1329 new_val = AddWithCarry(reg_size, | |
1330 instr->FlagsUpdate(), | |
1331 reg(reg_size, instr->Rn()), | |
1332 op2, | |
1333 nzcv().C()); | |
1334 | |
1335 set_reg(reg_size, instr->Rd(), new_val); | |
1336 } | 1336 } |
1337 | 1337 |
1338 | 1338 |
1339 void Simulator::VisitLogicalShifted(Instruction* instr) { | 1339 void Simulator::VisitLogicalShifted(Instruction* instr) { |
1340 unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits | |
1341 : kWRegSizeInBits; | |
1342 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); | 1340 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); |
1343 unsigned shift_amount = instr->ImmDPShift(); | 1341 unsigned shift_amount = instr->ImmDPShift(); |
1344 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type, | 1342 |
1345 shift_amount); | 1343 if (instr->SixtyFourBits()) { |
1346 if (instr->Mask(NOT) == NOT) { | 1344 int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); |
1347 op2 = ~op2; | 1345 op2 = (instr->Mask(NOT) == NOT) ? ~op2 : op2; |
1346 LogicalHelper<int64_t>(instr, op2); | |
1347 } else { | |
1348 int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); | |
1349 op2 = (instr->Mask(NOT) == NOT) ? ~op2 : op2; | |
1350 LogicalHelper<int32_t>(instr, op2); | |
1348 } | 1351 } |
1349 LogicalHelper(instr, op2); | |
1350 } | 1352 } |
1351 | 1353 |
1352 | 1354 |
1353 void Simulator::VisitLogicalImmediate(Instruction* instr) { | 1355 void Simulator::VisitLogicalImmediate(Instruction* instr) { |
1354 LogicalHelper(instr, instr->ImmLogical()); | 1356 if (instr->SixtyFourBits()) { |
1357 LogicalHelper<int64_t>(instr, instr->ImmLogical()); | |
1358 } else { | |
1359 LogicalHelper<int32_t>(instr, instr->ImmLogical()); | |
1360 } | |
1355 } | 1361 } |
1356 | 1362 |
1357 | 1363 |
1358 void Simulator::LogicalHelper(Instruction* instr, int64_t op2) { | 1364 template<typename T> |
1359 unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits | 1365 void Simulator::LogicalHelper(Instruction* instr, T op2) { |
1360 : kWRegSizeInBits; | 1366 T op1 = reg<T>(instr->Rn()); |
1361 int64_t op1 = reg(reg_size, instr->Rn()); | 1367 T result = 0; |
1362 int64_t result = 0; | |
1363 bool update_flags = false; | 1368 bool update_flags = false; |
1364 | 1369 |
1365 // Switch on the logical operation, stripping out the NOT bit, as it has a | 1370 // Switch on the logical operation, stripping out the NOT bit, as it has a |
1366 // different meaning for logical immediate instructions. | 1371 // different meaning for logical immediate instructions. |
1367 switch (instr->Mask(LogicalOpMask & ~NOT)) { | 1372 switch (instr->Mask(LogicalOpMask & ~NOT)) { |
1368 case ANDS: update_flags = true; // Fall through. | 1373 case ANDS: update_flags = true; // Fall through. |
1369 case AND: result = op1 & op2; break; | 1374 case AND: result = op1 & op2; break; |
1370 case ORR: result = op1 | op2; break; | 1375 case ORR: result = op1 | op2; break; |
1371 case EOR: result = op1 ^ op2; break; | 1376 case EOR: result = op1 ^ op2; break; |
1372 default: | 1377 default: |
1373 UNIMPLEMENTED(); | 1378 UNIMPLEMENTED(); |
1374 } | 1379 } |
1375 | 1380 |
1376 if (update_flags) { | 1381 if (update_flags) { |
1377 nzcv().SetN(CalcNFlag(result, reg_size)); | 1382 nzcv().SetN(CalcNFlag(result)); |
1378 nzcv().SetZ(CalcZFlag(result)); | 1383 nzcv().SetZ(CalcZFlag(result)); |
1379 nzcv().SetC(0); | 1384 nzcv().SetC(0); |
1380 nzcv().SetV(0); | 1385 nzcv().SetV(0); |
1381 } | 1386 } |
1382 | 1387 |
1383 set_reg(reg_size, instr->Rd(), result, instr->RdMode()); | 1388 set_reg<T>(instr->Rd(), result, instr->RdMode()); |
1384 } | 1389 } |
1385 | 1390 |
1386 | 1391 |
1387 void Simulator::VisitConditionalCompareRegister(Instruction* instr) { | 1392 void Simulator::VisitConditionalCompareRegister(Instruction* instr) { |
1388 unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits | 1393 if (instr->SixtyFourBits()) { |
1389 : kWRegSizeInBits; | 1394 ConditionalCompareHelper(instr, xreg(instr->Rm())); |
1390 ConditionalCompareHelper(instr, reg(reg_size, instr->Rm())); | 1395 } else { |
1396 ConditionalCompareHelper(instr, wreg(instr->Rm())); | |
1397 } | |
1391 } | 1398 } |
1392 | 1399 |
1393 | 1400 |
1394 void Simulator::VisitConditionalCompareImmediate(Instruction* instr) { | 1401 void Simulator::VisitConditionalCompareImmediate(Instruction* instr) { |
1395 ConditionalCompareHelper(instr, instr->ImmCondCmp()); | 1402 if (instr->SixtyFourBits()) { |
1403 ConditionalCompareHelper<int64_t>(instr, instr->ImmCondCmp()); | |
1404 } else { | |
1405 ConditionalCompareHelper<int32_t>(instr, instr->ImmCondCmp()); | |
1406 } | |
1396 } | 1407 } |
1397 | 1408 |
1398 | 1409 |
1399 void Simulator::ConditionalCompareHelper(Instruction* instr, int64_t op2) { | 1410 template<typename T> |
1400 unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits | 1411 void Simulator::ConditionalCompareHelper(Instruction* instr, T op2) { |
1401 : kWRegSizeInBits; | 1412 T op1 = reg<T>(instr->Rn()); |
1402 int64_t op1 = reg(reg_size, instr->Rn()); | |
1403 | 1413 |
1404 if (ConditionPassed(static_cast<Condition>(instr->Condition()))) { | 1414 if (ConditionPassed(static_cast<Condition>(instr->Condition()))) { |
1405 // If the condition passes, set the status flags to the result of comparing | 1415 // If the condition passes, set the status flags to the result of comparing |
1406 // the operands. | 1416 // the operands. |
1407 if (instr->Mask(ConditionalCompareMask) == CCMP) { | 1417 if (instr->Mask(ConditionalCompareMask) == CCMP) { |
1408 AddWithCarry(reg_size, true, op1, ~op2, 1); | 1418 AddWithCarry<T>(true, op1, ~op2, 1); |
1409 } else { | 1419 } else { |
1410 ASSERT(instr->Mask(ConditionalCompareMask) == CCMN); | 1420 ASSERT(instr->Mask(ConditionalCompareMask) == CCMN); |
1411 AddWithCarry(reg_size, true, op1, op2, 0); | 1421 AddWithCarry<T>(true, op1, op2, 0); |
1412 } | 1422 } |
1413 } else { | 1423 } else { |
1414 // If the condition fails, set the status flags to the nzcv immediate. | 1424 // If the condition fails, set the status flags to the nzcv immediate. |
1415 nzcv().SetFlags(instr->Nzcv()); | 1425 nzcv().SetFlags(instr->Nzcv()); |
1416 } | 1426 } |
1417 } | 1427 } |
1418 | 1428 |
1419 | 1429 |
1420 void Simulator::VisitLoadStoreUnsignedOffset(Instruction* instr) { | 1430 void Simulator::VisitLoadStoreUnsignedOffset(Instruction* instr) { |
1421 int offset = instr->ImmLSUnsigned() << instr->SizeLS(); | 1431 int offset = instr->ImmLSUnsigned() << instr->SizeLS(); |
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1436 void Simulator::VisitLoadStorePostIndex(Instruction* instr) { | 1446 void Simulator::VisitLoadStorePostIndex(Instruction* instr) { |
1437 LoadStoreHelper(instr, instr->ImmLS(), PostIndex); | 1447 LoadStoreHelper(instr, instr->ImmLS(), PostIndex); |
1438 } | 1448 } |
1439 | 1449 |
1440 | 1450 |
1441 void Simulator::VisitLoadStoreRegisterOffset(Instruction* instr) { | 1451 void Simulator::VisitLoadStoreRegisterOffset(Instruction* instr) { |
1442 Extend ext = static_cast<Extend>(instr->ExtendMode()); | 1452 Extend ext = static_cast<Extend>(instr->ExtendMode()); |
1443 ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); | 1453 ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); |
1444 unsigned shift_amount = instr->ImmShiftLS() * instr->SizeLS(); | 1454 unsigned shift_amount = instr->ImmShiftLS() * instr->SizeLS(); |
1445 | 1455 |
1446 int64_t offset = ExtendValue(kXRegSizeInBits, xreg(instr->Rm()), ext, | 1456 int64_t offset = ExtendValue(xreg(instr->Rm()), ext, shift_amount); |
1447 shift_amount); | |
1448 LoadStoreHelper(instr, offset, Offset); | 1457 LoadStoreHelper(instr, offset, Offset); |
1449 } | 1458 } |
1450 | 1459 |
1451 | 1460 |
1452 void Simulator::LoadStoreHelper(Instruction* instr, | 1461 void Simulator::LoadStoreHelper(Instruction* instr, |
1453 int64_t offset, | 1462 int64_t offset, |
1454 AddrMode addrmode) { | 1463 AddrMode addrmode) { |
1455 unsigned srcdst = instr->Rt(); | 1464 unsigned srcdst = instr->Rt(); |
1456 unsigned addr_reg = instr->Rn(); | 1465 unsigned addr_reg = instr->Rn(); |
1457 uint8_t* address = LoadStoreAddress(addr_reg, offset, addrmode); | 1466 uint8_t* address = LoadStoreAddress(addr_reg, offset, addrmode); |
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1477 switch (op) { | 1486 switch (op) { |
1478 case LDRB_w: | 1487 case LDRB_w: |
1479 case LDRH_w: | 1488 case LDRH_w: |
1480 case LDR_w: | 1489 case LDR_w: |
1481 case LDR_x: set_xreg(srcdst, MemoryRead(address, num_bytes)); break; | 1490 case LDR_x: set_xreg(srcdst, MemoryRead(address, num_bytes)); break; |
1482 case STRB_w: | 1491 case STRB_w: |
1483 case STRH_w: | 1492 case STRH_w: |
1484 case STR_w: | 1493 case STR_w: |
1485 case STR_x: MemoryWrite(address, xreg(srcdst), num_bytes); break; | 1494 case STR_x: MemoryWrite(address, xreg(srcdst), num_bytes); break; |
1486 case LDRSB_w: { | 1495 case LDRSB_w: { |
1487 set_wreg(srcdst, | 1496 set_wreg(srcdst, ExtendValue<int32_t>(MemoryRead8(address), SXTB)); |
1488 ExtendValue(kWRegSizeInBits, MemoryRead8(address), SXTB)); | |
1489 break; | 1497 break; |
1490 } | 1498 } |
1491 case LDRSB_x: { | 1499 case LDRSB_x: { |
1492 set_xreg(srcdst, | 1500 set_xreg(srcdst, ExtendValue<int64_t>(MemoryRead8(address), SXTB)); |
1493 ExtendValue(kXRegSizeInBits, MemoryRead8(address), SXTB)); | |
1494 break; | 1501 break; |
1495 } | 1502 } |
1496 case LDRSH_w: { | 1503 case LDRSH_w: { |
1497 set_wreg(srcdst, | 1504 set_wreg(srcdst, ExtendValue<int32_t>(MemoryRead16(address), SXTH)); |
1498 ExtendValue(kWRegSizeInBits, MemoryRead16(address), SXTH)); | |
1499 break; | 1505 break; |
1500 } | 1506 } |
1501 case LDRSH_x: { | 1507 case LDRSH_x: { |
1502 set_xreg(srcdst, | 1508 set_xreg(srcdst, ExtendValue<int64_t>(MemoryRead16(address), SXTH)); |
1503 ExtendValue(kXRegSizeInBits, MemoryRead16(address), SXTH)); | |
1504 break; | 1509 break; |
1505 } | 1510 } |
1506 case LDRSW_x: { | 1511 case LDRSW_x: { |
1507 set_xreg(srcdst, | 1512 set_xreg(srcdst, ExtendValue<int64_t>(MemoryRead32(address), SXTW)); |
1508 ExtendValue(kXRegSizeInBits, MemoryRead32(address), SXTW)); | |
1509 break; | 1513 break; |
1510 } | 1514 } |
1511 case LDR_s: set_sreg(srcdst, MemoryReadFP32(address)); break; | 1515 case LDR_s: set_sreg(srcdst, MemoryReadFP32(address)); break; |
1512 case LDR_d: set_dreg(srcdst, MemoryReadFP64(address)); break; | 1516 case LDR_d: set_dreg(srcdst, MemoryReadFP64(address)); break; |
1513 case STR_s: MemoryWriteFP32(address, sreg(srcdst)); break; | 1517 case STR_s: MemoryWriteFP32(address, sreg(srcdst)); break; |
1514 case STR_d: MemoryWriteFP64(address, dreg(srcdst)); break; | 1518 case STR_d: MemoryWriteFP64(address, dreg(srcdst)); break; |
1515 default: UNIMPLEMENTED(); | 1519 default: UNIMPLEMENTED(); |
1516 } | 1520 } |
1517 | 1521 |
1518 // Handle the writeback for loads after the load to ensure safe pop | 1522 // Handle the writeback for loads after the load to ensure safe pop |
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1598 set_xreg(rt, MemoryRead64(address)); | 1602 set_xreg(rt, MemoryRead64(address)); |
1599 set_xreg(rt2, MemoryRead64(address + kXRegSize)); | 1603 set_xreg(rt2, MemoryRead64(address + kXRegSize)); |
1600 break; | 1604 break; |
1601 } | 1605 } |
1602 case LDP_d: { | 1606 case LDP_d: { |
1603 set_dreg(rt, MemoryReadFP64(address)); | 1607 set_dreg(rt, MemoryReadFP64(address)); |
1604 set_dreg(rt2, MemoryReadFP64(address + kDRegSize)); | 1608 set_dreg(rt2, MemoryReadFP64(address + kDRegSize)); |
1605 break; | 1609 break; |
1606 } | 1610 } |
1607 case LDPSW_x: { | 1611 case LDPSW_x: { |
1608 set_xreg(rt, ExtendValue(kXRegSizeInBits, MemoryRead32(address), SXTW)); | 1612 set_xreg(rt, ExtendValue<int64_t>(MemoryRead32(address), SXTW)); |
1609 set_xreg(rt2, ExtendValue(kXRegSizeInBits, | 1613 set_xreg(rt2, ExtendValue<int64_t>( |
1610 MemoryRead32(address + kWRegSize), SXTW)); | 1614 MemoryRead32(address + kWRegSize), SXTW)); |
1611 break; | 1615 break; |
1612 } | 1616 } |
1613 case STP_w: { | 1617 case STP_w: { |
1614 MemoryWrite32(address, wreg(rt)); | 1618 MemoryWrite32(address, wreg(rt)); |
1615 MemoryWrite32(address + kWRegSize, wreg(rt2)); | 1619 MemoryWrite32(address + kWRegSize, wreg(rt2)); |
1616 break; | 1620 break; |
1617 } | 1621 } |
1618 case STP_s: { | 1622 case STP_s: { |
1619 MemoryWriteFP32(address, sreg(rt)); | 1623 MemoryWriteFP32(address, sreg(rt)); |
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1815 default: | 1819 default: |
1816 UNREACHABLE(); | 1820 UNREACHABLE(); |
1817 } | 1821 } |
1818 | 1822 |
1819 // Update the destination register. | 1823 // Update the destination register. |
1820 set_xreg(instr->Rd(), new_xn_val); | 1824 set_xreg(instr->Rd(), new_xn_val); |
1821 } | 1825 } |
1822 | 1826 |
1823 | 1827 |
1824 void Simulator::VisitConditionalSelect(Instruction* instr) { | 1828 void Simulator::VisitConditionalSelect(Instruction* instr) { |
1825 uint64_t new_val = xreg(instr->Rn()); | |
1826 | |
1827 if (ConditionFailed(static_cast<Condition>(instr->Condition()))) { | 1829 if (ConditionFailed(static_cast<Condition>(instr->Condition()))) { |
1828 new_val = xreg(instr->Rm()); | 1830 uint64_t new_val = xreg(instr->Rm()); |
1829 switch (instr->Mask(ConditionalSelectMask)) { | 1831 switch (instr->Mask(ConditionalSelectMask)) { |
1830 case CSEL_w: | 1832 case CSEL_w: set_wreg(instr->Rd(), new_val); break; |
1831 case CSEL_x: break; | 1833 case CSEL_x: set_xreg(instr->Rd(), new_val); break; |
1832 case CSINC_w: | 1834 case CSINC_w: set_wreg(instr->Rd(), new_val + 1); break; |
1833 case CSINC_x: new_val++; break; | 1835 case CSINC_x: set_xreg(instr->Rd(), new_val + 1); break; |
1834 case CSINV_w: | 1836 case CSINV_w: set_wreg(instr->Rd(), ~new_val); break; |
1835 case CSINV_x: new_val = ~new_val; break; | 1837 case CSINV_x: set_xreg(instr->Rd(), ~new_val); break; |
1836 case CSNEG_w: | 1838 case CSNEG_w: set_wreg(instr->Rd(), -new_val); break; |
1837 case CSNEG_x: new_val = -new_val; break; | 1839 case CSNEG_x: set_xreg(instr->Rd(), -new_val); break; |
1838 default: UNIMPLEMENTED(); | 1840 default: UNIMPLEMENTED(); |
1839 } | 1841 } |
1842 } else { | |
1843 if (instr->SixtyFourBits()) { | |
1844 set_xreg(instr->Rd(), xreg(instr->Rn())); | |
1845 } else { | |
1846 set_wreg(instr->Rd(), wreg(instr->Rn())); | |
1847 } | |
1840 } | 1848 } |
1841 unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits | |
1842 : kWRegSizeInBits; | |
1843 set_reg(reg_size, instr->Rd(), new_val); | |
1844 } | 1849 } |
1845 | 1850 |
1846 | 1851 |
1847 void Simulator::VisitDataProcessing1Source(Instruction* instr) { | 1852 void Simulator::VisitDataProcessing1Source(Instruction* instr) { |
1848 unsigned dst = instr->Rd(); | 1853 unsigned dst = instr->Rd(); |
1849 unsigned src = instr->Rn(); | 1854 unsigned src = instr->Rn(); |
1850 | 1855 |
1851 switch (instr->Mask(DataProcessing1SourceMask)) { | 1856 switch (instr->Mask(DataProcessing1SourceMask)) { |
1852 case RBIT_w: set_wreg(dst, ReverseBits(wreg(src), kWRegSizeInBits)); break; | 1857 case RBIT_w: set_wreg(dst, ReverseBits(wreg(src), kWRegSizeInBits)); break; |
1853 case RBIT_x: set_xreg(dst, ReverseBits(xreg(src), kXRegSizeInBits)); break; | 1858 case RBIT_x: set_xreg(dst, ReverseBits(xreg(src), kXRegSizeInBits)); break; |
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1904 {0, 1, 2, 3, 4, 5, 6, 7} }; | 1909 {0, 1, 2, 3, 4, 5, 6, 7} }; |
1905 uint64_t result = 0; | 1910 uint64_t result = 0; |
1906 for (int i = 0; i < 8; i++) { | 1911 for (int i = 0; i < 8; i++) { |
1907 result <<= 8; | 1912 result <<= 8; |
1908 result |= bytes[permute_table[mode][i]]; | 1913 result |= bytes[permute_table[mode][i]]; |
1909 } | 1914 } |
1910 return result; | 1915 return result; |
1911 } | 1916 } |
1912 | 1917 |
1913 | 1918 |
1914 void Simulator::VisitDataProcessing2Source(Instruction* instr) { | 1919 template <typename T> |
1920 void Simulator::DataProcessing2Source(Instruction* instr) { | |
1915 Shift shift_op = NO_SHIFT; | 1921 Shift shift_op = NO_SHIFT; |
1916 int64_t result = 0; | 1922 T result = 0; |
1917 switch (instr->Mask(DataProcessing2SourceMask)) { | 1923 switch (instr->Mask(DataProcessing2SourceMask)) { |
1918 case SDIV_w: { | 1924 case SDIV_w: |
1919 int32_t rn = wreg(instr->Rn()); | 1925 case SDIV_x: { |
1920 int32_t rm = wreg(instr->Rm()); | 1926 T rn = reg<T>(instr->Rn()); |
1921 if ((rn == kWMinInt) && (rm == -1)) { | 1927 T rm = reg<T>(instr->Rm()); |
1922 result = kWMinInt; | 1928 if ((rn == std::numeric_limits<T>::min()) && (rm == -1)) { |
1929 result = std::numeric_limits<T>::min(); | |
1923 } else if (rm == 0) { | 1930 } else if (rm == 0) { |
1924 // Division by zero can be trapped, but not on A-class processors. | 1931 // Division by zero can be trapped, but not on A-class processors. |
1925 result = 0; | 1932 result = 0; |
1926 } else { | |
1927 result = rn / rm; | |
1928 } | |
1929 break; | |
1930 } | |
1931 case SDIV_x: { | |
1932 int64_t rn = xreg(instr->Rn()); | |
1933 int64_t rm = xreg(instr->Rm()); | |
1934 if ((rn == kXMinInt) && (rm == -1)) { | |
1935 result = kXMinInt; | |
1936 } else if (rm == 0) { | |
1937 // Division by zero can be trapped, but not on A-class processors. | |
1938 result = 0; | |
1939 } else { | 1933 } else { |
1940 result = rn / rm; | 1934 result = rn / rm; |
1941 } | 1935 } |
1942 break; | 1936 break; |
1943 } | 1937 } |
1944 case UDIV_w: { | 1938 case UDIV_w: |
1945 uint32_t rn = static_cast<uint32_t>(wreg(instr->Rn())); | 1939 case UDIV_x: { |
1946 uint32_t rm = static_cast<uint32_t>(wreg(instr->Rm())); | 1940 typedef typename make_unsigned<T>::type unsignedT; |
1941 unsignedT rn = static_cast<unsignedT>(reg<T>(instr->Rn())); | |
1942 unsignedT rm = static_cast<unsignedT>(reg<T>(instr->Rm())); | |
1947 if (rm == 0) { | 1943 if (rm == 0) { |
1948 // Division by zero can be trapped, but not on A-class processors. | 1944 // Division by zero can be trapped, but not on A-class processors. |
1949 result = 0; | 1945 result = 0; |
1950 } else { | |
1951 result = rn / rm; | |
1952 } | |
1953 break; | |
1954 } | |
1955 case UDIV_x: { | |
1956 uint64_t rn = static_cast<uint64_t>(xreg(instr->Rn())); | |
1957 uint64_t rm = static_cast<uint64_t>(xreg(instr->Rm())); | |
1958 if (rm == 0) { | |
1959 // Division by zero can be trapped, but not on A-class processors. | |
1960 result = 0; | |
1961 } else { | 1946 } else { |
1962 result = rn / rm; | 1947 result = rn / rm; |
1963 } | 1948 } |
1964 break; | 1949 break; |
1965 } | 1950 } |
1966 case LSLV_w: | 1951 case LSLV_w: |
1967 case LSLV_x: shift_op = LSL; break; | 1952 case LSLV_x: shift_op = LSL; break; |
1968 case LSRV_w: | 1953 case LSRV_w: |
1969 case LSRV_x: shift_op = LSR; break; | 1954 case LSRV_x: shift_op = LSR; break; |
1970 case ASRV_w: | 1955 case ASRV_w: |
1971 case ASRV_x: shift_op = ASR; break; | 1956 case ASRV_x: shift_op = ASR; break; |
1972 case RORV_w: | 1957 case RORV_w: |
1973 case RORV_x: shift_op = ROR; break; | 1958 case RORV_x: shift_op = ROR; break; |
1974 default: UNIMPLEMENTED(); | 1959 default: UNIMPLEMENTED(); |
1975 } | 1960 } |
1976 | 1961 |
1977 unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits | |
1978 : kWRegSizeInBits; | |
1979 if (shift_op != NO_SHIFT) { | 1962 if (shift_op != NO_SHIFT) { |
1980 // Shift distance encoded in the least-significant five/six bits of the | 1963 // Shift distance encoded in the least-significant five/six bits of the |
1981 // register. | 1964 // register. |
1982 int mask = (instr->SixtyFourBits() == 1) ? kShiftAmountXRegMask | 1965 unsigned shift = wreg(instr->Rm()); |
1983 : kShiftAmountWRegMask; | 1966 if (sizeof(T) == kWRegSize) { |
1984 unsigned shift = wreg(instr->Rm()) & mask; | 1967 shift &= kShiftAmountWRegMask; |
1985 result = ShiftOperand(reg_size, reg(reg_size, instr->Rn()), shift_op, | 1968 } else { |
1986 shift); | 1969 shift &= kShiftAmountXRegMask; |
1970 } | |
1971 result = ShiftOperand(reg<T>(instr->Rn()), shift_op, shift); | |
1987 } | 1972 } |
1988 set_reg(reg_size, instr->Rd(), result); | 1973 set_reg<T>(instr->Rd(), result); |
1989 } | 1974 } |
1990 | 1975 |
1991 | 1976 |
1977 void Simulator::VisitDataProcessing2Source(Instruction* instr) { | |
1978 if (instr->SixtyFourBits()) { | |
1979 DataProcessing2Source<int64_t>(instr); | |
1980 } else { | |
1981 DataProcessing2Source<int32_t>(instr); | |
1982 } | |
1983 } | |
1984 | |
1985 | |
1992 // The algorithm used is described in section 8.2 of | 1986 // The algorithm used is described in section 8.2 of |
1993 // Hacker's Delight, by Henry S. Warren, Jr. | 1987 // Hacker's Delight, by Henry S. Warren, Jr. |
1994 // It assumes that a right shift on a signed integer is an arithmetic shift. | 1988 // It assumes that a right shift on a signed integer is an arithmetic shift. |
1995 static int64_t MultiplyHighSigned(int64_t u, int64_t v) { | 1989 static int64_t MultiplyHighSigned(int64_t u, int64_t v) { |
1996 uint64_t u0, v0, w0; | 1990 uint64_t u0, v0, w0; |
1997 int64_t u1, v1, w1, w2, t; | 1991 int64_t u1, v1, w1, w2, t; |
1998 | 1992 |
1999 u0 = u & 0xffffffffL; | 1993 u0 = u & 0xffffffffL; |
2000 u1 = u >> 32; | 1994 u1 = u >> 32; |
2001 v0 = v & 0xffffffffL; | 1995 v0 = v & 0xffffffffL; |
2002 v1 = v >> 32; | 1996 v1 = v >> 32; |
2003 | 1997 |
2004 w0 = u0 * v0; | 1998 w0 = u0 * v0; |
2005 t = u1 * v0 + (w0 >> 32); | 1999 t = u1 * v0 + (w0 >> 32); |
2006 w1 = t & 0xffffffffL; | 2000 w1 = t & 0xffffffffL; |
2007 w2 = t >> 32; | 2001 w2 = t >> 32; |
2008 w1 = u0 * v1 + w1; | 2002 w1 = u0 * v1 + w1; |
2009 | 2003 |
2010 return u1 * v1 + w2 + (w1 >> 32); | 2004 return u1 * v1 + w2 + (w1 >> 32); |
2011 } | 2005 } |
2012 | 2006 |
2013 | 2007 |
2014 void Simulator::VisitDataProcessing3Source(Instruction* instr) { | 2008 void Simulator::VisitDataProcessing3Source(Instruction* instr) { |
2015 unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits | |
2016 : kWRegSizeInBits; | |
2017 | |
2018 int64_t result = 0; | 2009 int64_t result = 0; |
2019 // Extract and sign- or zero-extend 32-bit arguments for widening operations. | 2010 // Extract and sign- or zero-extend 32-bit arguments for widening operations. |
2020 uint64_t rn_u32 = reg<uint32_t>(instr->Rn()); | 2011 uint64_t rn_u32 = reg<uint32_t>(instr->Rn()); |
2021 uint64_t rm_u32 = reg<uint32_t>(instr->Rm()); | 2012 uint64_t rm_u32 = reg<uint32_t>(instr->Rm()); |
2022 int64_t rn_s32 = reg<int32_t>(instr->Rn()); | 2013 int64_t rn_s32 = reg<int32_t>(instr->Rn()); |
2023 int64_t rm_s32 = reg<int32_t>(instr->Rm()); | 2014 int64_t rm_s32 = reg<int32_t>(instr->Rm()); |
2024 switch (instr->Mask(DataProcessing3SourceMask)) { | 2015 switch (instr->Mask(DataProcessing3SourceMask)) { |
2025 case MADD_w: | 2016 case MADD_w: |
2026 case MADD_x: | 2017 case MADD_x: |
2027 result = xreg(instr->Ra()) + (xreg(instr->Rn()) * xreg(instr->Rm())); | 2018 result = xreg(instr->Ra()) + (xreg(instr->Rn()) * xreg(instr->Rm())); |
2028 break; | 2019 break; |
2029 case MSUB_w: | 2020 case MSUB_w: |
2030 case MSUB_x: | 2021 case MSUB_x: |
2031 result = xreg(instr->Ra()) - (xreg(instr->Rn()) * xreg(instr->Rm())); | 2022 result = xreg(instr->Ra()) - (xreg(instr->Rn()) * xreg(instr->Rm())); |
2032 break; | 2023 break; |
2033 case SMADDL_x: result = xreg(instr->Ra()) + (rn_s32 * rm_s32); break; | 2024 case SMADDL_x: result = xreg(instr->Ra()) + (rn_s32 * rm_s32); break; |
2034 case SMSUBL_x: result = xreg(instr->Ra()) - (rn_s32 * rm_s32); break; | 2025 case SMSUBL_x: result = xreg(instr->Ra()) - (rn_s32 * rm_s32); break; |
2035 case UMADDL_x: result = xreg(instr->Ra()) + (rn_u32 * rm_u32); break; | 2026 case UMADDL_x: result = xreg(instr->Ra()) + (rn_u32 * rm_u32); break; |
2036 case UMSUBL_x: result = xreg(instr->Ra()) - (rn_u32 * rm_u32); break; | 2027 case UMSUBL_x: result = xreg(instr->Ra()) - (rn_u32 * rm_u32); break; |
2037 case SMULH_x: | 2028 case SMULH_x: |
2038 ASSERT(instr->Ra() == kZeroRegCode); | 2029 ASSERT(instr->Ra() == kZeroRegCode); |
2039 result = MultiplyHighSigned(xreg(instr->Rn()), xreg(instr->Rm())); | 2030 result = MultiplyHighSigned(xreg(instr->Rn()), xreg(instr->Rm())); |
2040 break; | 2031 break; |
2041 default: UNIMPLEMENTED(); | 2032 default: UNIMPLEMENTED(); |
2042 } | 2033 } |
2043 set_reg(reg_size, instr->Rd(), result); | 2034 |
2035 if (instr->SixtyFourBits()) { | |
2036 set_xreg(instr->Rd(), result); | |
2037 } else { | |
2038 set_wreg(instr->Rd(), result); | |
2039 } | |
2044 } | 2040 } |
2045 | 2041 |
2046 | 2042 |
2047 void Simulator::VisitBitfield(Instruction* instr) { | 2043 template <typename T> |
2048 unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits | 2044 void Simulator::BitfieldHelper(Instruction* instr) { |
2049 : kWRegSizeInBits; | 2045 typedef typename make_unsigned<T>::type unsignedT; |
2050 int64_t reg_mask = instr->SixtyFourBits() ? kXRegMask : kWRegMask; | 2046 T reg_size = sizeof(T) * 8; |
2051 int64_t R = instr->ImmR(); | 2047 T R = instr->ImmR(); |
2052 int64_t S = instr->ImmS(); | 2048 T S = instr->ImmS(); |
2053 int64_t diff = S - R; | 2049 T diff = S - R; |
2054 int64_t mask; | 2050 T mask; |
2055 if (diff >= 0) { | 2051 if (diff >= 0) { |
2056 mask = diff < reg_size - 1 ? (1L << (diff + 1)) - 1 | 2052 mask = diff < reg_size - 1 ? (static_cast<T>(1) << (diff + 1)) - 1 |
2057 : reg_mask; | 2053 : static_cast<T>(-1); |
2058 } else { | 2054 } else { |
2059 mask = ((1L << (S + 1)) - 1); | 2055 mask = ((1L << (S + 1)) - 1); |
2060 mask = (static_cast<uint64_t>(mask) >> R) | (mask << (reg_size - R)); | 2056 mask = (static_cast<uint64_t>(mask) >> R) | (mask << (reg_size - R)); |
2061 diff += reg_size; | 2057 diff += reg_size; |
2062 } | 2058 } |
2063 | 2059 |
2064 // inzero indicates if the extracted bitfield is inserted into the | 2060 // inzero indicates if the extracted bitfield is inserted into the |
2065 // destination register value or in zero. | 2061 // destination register value or in zero. |
2066 // If extend is true, extend the sign of the extracted bitfield. | 2062 // If extend is true, extend the sign of the extracted bitfield. |
2067 bool inzero = false; | 2063 bool inzero = false; |
2068 bool extend = false; | 2064 bool extend = false; |
2069 switch (instr->Mask(BitfieldMask)) { | 2065 switch (instr->Mask(BitfieldMask)) { |
2070 case BFM_x: | 2066 case BFM_x: |
2071 case BFM_w: | 2067 case BFM_w: |
2072 break; | 2068 break; |
2073 case SBFM_x: | 2069 case SBFM_x: |
2074 case SBFM_w: | 2070 case SBFM_w: |
2075 inzero = true; | 2071 inzero = true; |
2076 extend = true; | 2072 extend = true; |
2077 break; | 2073 break; |
2078 case UBFM_x: | 2074 case UBFM_x: |
2079 case UBFM_w: | 2075 case UBFM_w: |
2080 inzero = true; | 2076 inzero = true; |
2081 break; | 2077 break; |
2082 default: | 2078 default: |
2083 UNIMPLEMENTED(); | 2079 UNIMPLEMENTED(); |
2084 } | 2080 } |
2085 | 2081 |
2086 int64_t dst = inzero ? 0 : reg(reg_size, instr->Rd()); | 2082 T dst = inzero ? 0 : reg<T>(instr->Rd()); |
2087 int64_t src = reg(reg_size, instr->Rn()); | 2083 T src = reg<T>(instr->Rn()); |
2088 // Rotate source bitfield into place. | 2084 // Rotate source bitfield into place. |
2089 int64_t result = (static_cast<uint64_t>(src) >> R) | (src << (reg_size - R)); | 2085 T result = (static_cast<unsignedT>(src) >> R) | (src << (reg_size - R)); |
2090 // Determine the sign extension. | 2086 // Determine the sign extension. |
2091 int64_t topbits_preshift = (1L << (reg_size - diff - 1)) - 1; | 2087 T topbits_preshift = (static_cast<T>(1) << (reg_size - diff - 1)) - 1; |
2092 int64_t signbits = (extend && ((src >> S) & 1) ? topbits_preshift : 0) | 2088 T signbits = (extend && ((src >> S) & 1) ? topbits_preshift : 0) |
2093 << (diff + 1); | 2089 << (diff + 1); |
2094 | 2090 |
2095 // Merge sign extension, dest/zero and bitfield. | 2091 // Merge sign extension, dest/zero and bitfield. |
2096 result = signbits | (result & mask) | (dst & ~mask); | 2092 result = signbits | (result & mask) | (dst & ~mask); |
2097 | 2093 |
2098 set_reg(reg_size, instr->Rd(), result); | 2094 set_reg<T>(instr->Rd(), result); |
2095 } | |
2096 | |
2097 | |
2098 void Simulator::VisitBitfield(Instruction* instr) { | |
2099 if (instr->SixtyFourBits()) { | |
2100 BitfieldHelper<int64_t>(instr); | |
2101 } else { | |
2102 BitfieldHelper<int32_t>(instr); | |
2103 } | |
2099 } | 2104 } |
2100 | 2105 |
2101 | 2106 |
2102 void Simulator::VisitExtract(Instruction* instr) { | 2107 void Simulator::VisitExtract(Instruction* instr) { |
2103 unsigned lsb = instr->ImmS(); | 2108 if (instr->SixtyFourBits()) { |
2104 unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits | 2109 Extract<uint64_t>(instr); |
2105 : kWRegSizeInBits; | 2110 } else { |
2106 uint64_t result = reg(reg_size, instr->Rm()); | 2111 Extract<uint32_t>(instr); |
2107 if (lsb) { | |
2108 result = (result >> lsb) | (reg(reg_size, instr->Rn()) << (reg_size - lsb)); | |
2109 } | 2112 } |
2110 | |
2111 set_reg(reg_size, instr->Rd(), result); | |
2112 } | 2113 } |
2113 | 2114 |
2114 | 2115 |
2115 void Simulator::VisitFPImmediate(Instruction* instr) { | 2116 void Simulator::VisitFPImmediate(Instruction* instr) { |
2116 AssertSupportedFPCR(); | 2117 AssertSupportedFPCR(); |
2117 | 2118 |
2118 unsigned dest = instr->Rd(); | 2119 unsigned dest = instr->Rd(); |
2119 switch (instr->Mask(FPImmediateMask)) { | 2120 switch (instr->Mask(FPImmediateMask)) { |
2120 case FMOV_s_imm: set_sreg(dest, instr->ImmFP32()); break; | 2121 case FMOV_s_imm: set_sreg(dest, instr->ImmFP32()); break; |
2121 case FMOV_d_imm: set_dreg(dest, instr->ImmFP64()); break; | 2122 case FMOV_d_imm: set_dreg(dest, instr->ImmFP64()); break; |
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3726 | 3727 |
3727 delete[] format; | 3728 delete[] format; |
3728 } | 3729 } |
3729 | 3730 |
3730 | 3731 |
3731 #endif // USE_SIMULATOR | 3732 #endif // USE_SIMULATOR |
3732 | 3733 |
3733 } } // namespace v8::internal | 3734 } } // namespace v8::internal |
3734 | 3735 |
3735 #endif // V8_TARGET_ARCH_ARM64 | 3736 #endif // V8_TARGET_ARCH_ARM64 |
OLD | NEW |