Change arm64 simulator register backing store.

src/arm64/simulator-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <stdlib.h>
 #include <cmath>
 #include <cstdarg>
 #include "v8.h"
 
 #if V8_TARGET_ARCH_ARM64
@@ skipping 805 matching lines @@
     }
   }
   if ((strcmp("csp", name) == 0) || (strcmp("wcsp", name) == 0)) {
     return kSPRegInternalCode;
   }
   return -1;
 }
 
 
 // Helpers ---------------------------------------------------------------------
-int64_t Simulator::AddWithCarry(unsigned reg_size,
-                                bool set_flags,
-                                int64_t src1,
-                                int64_t src2,
-                                int64_t carry_in) {
+template<> struct make_unsigned<int32_t> {
+  typedef uint32_t type;
+};
+
+
+template<> struct make_unsigned<int64_t> {
+  typedef uint64_t type;
+};
+
+
+template <typename T>
+T Simulator::AddWithCarry(bool set_flags,
+                          T src1,
+                          T src2,
+                          T carry_in) {
+  typedef typename make_unsigned<T>::type unsignedT;
   ASSERT((carry_in == 0) || (carry_in == 1));
-  ASSERT((reg_size == kXRegSizeInBits) || (reg_size == kWRegSizeInBits));
 
-  uint64_t u1, u2;
-  int64_t result;
-  int64_t signed_sum = src1 + src2 + carry_in;
+  T signed_sum = src1 + src2 + carry_in;
+  T result = signed_sum;
 
   bool N, Z, C, V;
+  unsignedT u1 = static_cast<unsignedT>(src1);
+  unsignedT u2 = static_cast<unsignedT>(src2);
 
-  if (reg_size == kWRegSizeInBits) {
-    u1 = static_cast<uint64_t>(src1) & kWRegMask;
-    u2 = static_cast<uint64_t>(src2) & kWRegMask;
+  // Compute the C flag by comparing the sum to the max unsigned integer.
+  C = ((std::numeric_limits<unsignedT>::max() - u1) < (u2 + carry_in)) ||
+      ((std::numeric_limits<unsignedT>::max() - u1 - carry_in) < u2);
+  // Overflow iff the sign bit is the same for the two inputs and different
+  // for the result.
+  V = ((src1 ^ src2) >= 0) && ((src1 ^ result) < 0);
 
-    result = signed_sum & kWRegMask;
-    // Compute the C flag by comparing the sum to the max unsigned integer.
-    C = ((kWMaxUInt - u1) < (u2 + carry_in)) ||
-        ((kWMaxUInt - u1 - carry_in) < u2);
-    // Overflow iff the sign bit is the same for the two inputs and different
-    // for the result.
-    int64_t s_src1 = src1 << (kXRegSizeInBits - kWRegSizeInBits);
-    int64_t s_src2 = src2 << (kXRegSizeInBits - kWRegSizeInBits);
-    int64_t s_result = result << (kXRegSizeInBits - kWRegSizeInBits);
-    V = ((s_src1 ^ s_src2) >= 0) && ((s_src1 ^ s_result) < 0);
-
-  } else {
-    u1 = static_cast<uint64_t>(src1);
-    u2 = static_cast<uint64_t>(src2);
-
-    result = signed_sum;
-    // Compute the C flag by comparing the sum to the max unsigned integer.
-    C = ((kXMaxUInt - u1) < (u2 + carry_in)) ||
-        ((kXMaxUInt - u1 - carry_in) < u2);
-    // Overflow iff the sign bit is the same for the two inputs and different
-    // for the result.
-    V = ((src1 ^ src2) >= 0) && ((src1 ^ result) < 0);
-  }
-
-  N = CalcNFlag(result, reg_size);
+  N = CalcNFlag(result);
   Z = CalcZFlag(result);
 
   if (set_flags) {
     nzcv().SetN(N);
     nzcv().SetZ(Z);
     nzcv().SetC(C);
     nzcv().SetV(V);
   }
   return result;
 }
 
 
-int64_t Simulator::ShiftOperand(unsigned reg_size,
-                                int64_t value,
-                                Shift shift_type,
-                                unsigned amount) {
+template<typename T>
+void Simulator::AddSubWithCarry(Instruction* instr) {
+  T op2 = reg<T>(instr->Rm());
+  T new_val;
+
+  if ((instr->Mask(AddSubOpMask) == SUB) || instr->Mask(AddSubOpMask) == SUBS) {
+    op2 = ~op2;
+  }
+
+  new_val = AddWithCarry<T>(instr->FlagsUpdate(),
+                            reg<T>(instr->Rn()),
+                            op2,
+                            nzcv().C());
+
+  set_reg<T>(instr->Rd(), new_val);
+}
+
+template <typename T>
+T Simulator::ShiftOperand(T value, Shift shift_type, unsigned amount) {
+  typedef typename make_unsigned<T>::type unsignedT;
+
   if (amount == 0) {
     return value;
   }
-  int64_t mask = reg_size == kXRegSizeInBits ? kXRegMask : kWRegMask;
+
   switch (shift_type) {
     case LSL:
-      return (value << amount) & mask;
+      return value << amount;
     case LSR:
-      return static_cast<uint64_t>(value) >> amount;
-    case ASR: {
-      // Shift used to restore the sign.
-      unsigned s_shift = kXRegSizeInBits - reg_size;
-      // Value with its sign restored.
-      int64_t s_value = (value << s_shift) >> s_shift;
-      return (s_value >> amount) & mask;
-    }
-    case ROR: {
-      if (reg_size == kWRegSizeInBits) {
-        value &= kWRegMask;
-      }
-      return (static_cast<uint64_t>(value) >> amount) |
-             ((value & ((1L << amount) - 1L)) << (reg_size - amount));
-    }
+      return static_cast<unsignedT>(value) >> amount;
+    case ASR:
+      return value >> amount;
+    case ROR:
+      return (static_cast<unsignedT>(value) >> amount) |
+              ((value & ((1L << amount) - 1L)) <<
+                  (sizeof(unsignedT) * 8 - amount));
     default:
       UNIMPLEMENTED();
       return 0;
   }
 }
 
 
-int64_t Simulator::ExtendValue(unsigned reg_size,
-                               int64_t value,
-                               Extend extend_type,
-                               unsigned left_shift) {
+template <typename T>
+T Simulator::ExtendValue(T value, Extend extend_type, unsigned left_shift) {
+  const unsigned kSignExtendBShift = (sizeof(T) - 1) * 8;
+  const unsigned kSignExtendHShift = (sizeof(T) - 2) * 8;
+  const unsigned kSignExtendWShift = (sizeof(T) - 4) * 8;
+
   switch (extend_type) {
     case UXTB:
       value &= kByteMask;
       break;
     case UXTH:
       value &= kHalfWordMask;
       break;
     case UXTW:
       value &= kWordMask;
       break;
     case SXTB:
-      value = (value << 56) >> 56;
+      value = (value << kSignExtendBShift) >> kSignExtendBShift;
       break;
     case SXTH:
-      value = (value << 48) >> 48;
+      value = (value << kSignExtendHShift) >> kSignExtendHShift;
       break;
     case SXTW:
-      value = (value << 32) >> 32;
+      value = (value << kSignExtendWShift) >> kSignExtendWShift;
       break;
     case UXTX:
     case SXTX:
       break;
     default:
       UNREACHABLE();
   }
-  int64_t mask = (reg_size == kXRegSizeInBits) ? kXRegMask : kWRegMask;
-  return (value << left_shift) & mask;
+  return value << left_shift;
 }
 
 
+template <typename T>
+void Simulator::Extract(Instruction* instr) {
+  unsigned lsb = instr->ImmS();
+  T op2 = reg<T>(instr->Rm());
+  T result = op2;
+
+  if (lsb) {
+    T op1 = reg<T>(instr->Rn());
+    result = op2 >> lsb | (op1 << ((sizeof(T) * 8) - lsb));
+  }
+  set_reg<T>(instr->Rd(), result);
+}
+
+
 template<> double Simulator::FPDefaultNaN<double>() const {
   return kFP64DefaultNaN;
 }
 
 
 template<> float Simulator::FPDefaultNaN<float>() const {
   return kFP32DefaultNaN;
 }
 
 
@@ skipping 290 matching lines @@
     case CBNZ_w: take_branch = (wreg(rt) != 0); break;
     case CBNZ_x: take_branch = (xreg(rt) != 0); break;
     default: UNIMPLEMENTED();
   }
   if (take_branch) {
     set_pc(instr->ImmPCOffsetTarget());
   }
 }
 
 
-void Simulator::AddSubHelper(Instruction* instr, int64_t op2) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
-                                             : kWRegSizeInBits;
+template<typename T>
+void Simulator::AddSubHelper(Instruction* instr, T op2) {
   bool set_flags = instr->FlagsUpdate();
-  int64_t new_val = 0;
+  T new_val = 0;
   Instr operation = instr->Mask(AddSubOpMask);
 
   switch (operation) {
     case ADD:
     case ADDS: {
-      new_val = AddWithCarry(reg_size,
-                             set_flags,
-                             reg(reg_size, instr->Rn(), instr->RnMode()),
-                             op2);
+      new_val = AddWithCarry<T>(set_flags,
+                                reg<T>(instr->Rn(), instr->RnMode()),
+                                op2);
       break;
     }
     case SUB:
     case SUBS: {
-      new_val = AddWithCarry(reg_size,
-                             set_flags,
-                             reg(reg_size, instr->Rn(), instr->RnMode()),
-                             ~op2,
-                             1);
+      new_val = AddWithCarry<T>(set_flags,
+                                reg<T>(instr->Rn(), instr->RnMode()),
+                                ~op2,
+                                1);
       break;
     }
     default: UNREACHABLE();
   }
 
-  set_reg(reg_size, instr->Rd(), new_val, instr->RdMode());
+  set_reg<T>(instr->Rd(), new_val, instr->RdMode());
 }
 
 
 void Simulator::VisitAddSubShifted(Instruction* instr) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
-                                             : kWRegSizeInBits;
-  int64_t op2 = ShiftOperand(reg_size,
-                             reg(reg_size, instr->Rm()),
-                             static_cast<Shift>(instr->ShiftDP()),
-                             instr->ImmDPShift());
-  AddSubHelper(instr, op2);
+  Shift shift_type = static_cast<Shift>(instr->ShiftDP());
+  unsigned shift_amount = instr->ImmDPShift();
+
+  if (instr->SixtyFourBits()) {
+    int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount);
+    AddSubHelper(instr, op2);
+  } else {
+    int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount);
+    AddSubHelper(instr, op2);
+  }
 }
 
 
 void Simulator::VisitAddSubImmediate(Instruction* instr) {
   int64_t op2 = instr->ImmAddSub() << ((instr->ShiftAddSub() == 1) ? 12 : 0);
-  AddSubHelper(instr, op2);
+  if (instr->SixtyFourBits()) {
+    AddSubHelper<int64_t>(instr, op2);
+  } else {
+    AddSubHelper<int32_t>(instr, op2);
+  }
 }
 
 
 void Simulator::VisitAddSubExtended(Instruction* instr) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
-                                             : kWRegSizeInBits;
-  int64_t op2 = ExtendValue(reg_size,
-                            reg(reg_size, instr->Rm()),
-                            static_cast<Extend>(instr->ExtendMode()),
-                            instr->ImmExtendShift());
-  AddSubHelper(instr, op2);
+  Extend ext = static_cast<Extend>(instr->ExtendMode());
+  unsigned left_shift = instr->ImmExtendShift();
+  if (instr->SixtyFourBits()) {
+    int64_t op2 = ExtendValue(xreg(instr->Rm()), ext, left_shift);
+    AddSubHelper(instr, op2);
+  } else {
+    int32_t op2 = ExtendValue(wreg(instr->Rm()), ext, left_shift);
+    AddSubHelper(instr, op2);
+  }
 }
 
 
 void Simulator::VisitAddSubWithCarry(Instruction* instr) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
-                                             : kWRegSizeInBits;
-  int64_t op2 = reg(reg_size, instr->Rm());
-  int64_t new_val;
-
-  if ((instr->Mask(AddSubOpMask) == SUB) || instr->Mask(AddSubOpMask) == SUBS) {
-    op2 = ~op2;
+  if (instr->SixtyFourBits()) {
+    AddSubWithCarry<int64_t>(instr);
+  } else {
+    AddSubWithCarry<int32_t>(instr);
   }
-
-  new_val = AddWithCarry(reg_size,
-                         instr->FlagsUpdate(),
-                         reg(reg_size, instr->Rn()),
-                         op2,
-                         nzcv().C());
-
-  set_reg(reg_size, instr->Rd(), new_val);
 }
 
 
 void Simulator::VisitLogicalShifted(Instruction* instr) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
-                                             : kWRegSizeInBits;
   Shift shift_type = static_cast<Shift>(instr->ShiftDP());
   unsigned shift_amount = instr->ImmDPShift();
-  int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type,
-                             shift_amount);
-  if (instr->Mask(NOT) == NOT) {
-    op2 = ~op2;
+
+  if (instr->SixtyFourBits()) {
+    int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount);
+    op2 = (instr->Mask(NOT) == NOT) ? ~op2 : op2;
+    LogicalHelper<int64_t>(instr, op2);
+  } else {
+    int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount);
+    op2 = (instr->Mask(NOT) == NOT) ? ~op2 : op2;
+    LogicalHelper<int32_t>(instr, op2);
   }
-  LogicalHelper(instr, op2);
 }
 
 
 void Simulator::VisitLogicalImmediate(Instruction* instr) {
-  LogicalHelper(instr, instr->ImmLogical());
+  if (instr->SixtyFourBits()) {
+    LogicalHelper<int64_t>(instr, instr->ImmLogical());
+  } else {
+    LogicalHelper<int32_t>(instr, instr->ImmLogical());
+  }
 }
 
 
-void Simulator::LogicalHelper(Instruction* instr, int64_t op2) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
-                                             : kWRegSizeInBits;
-  int64_t op1 = reg(reg_size, instr->Rn());
-  int64_t result = 0;
+template<typename T>
+void Simulator::LogicalHelper(Instruction* instr, T op2) {
+  T op1 = reg<T>(instr->Rn());
+  T result = 0;
   bool update_flags = false;
 
   // Switch on the logical operation, stripping out the NOT bit, as it has a
   // different meaning for logical immediate instructions.
   switch (instr->Mask(LogicalOpMask & ~NOT)) {
     case ANDS: update_flags = true;  // Fall through.
     case AND: result = op1 & op2; break;
     case ORR: result = op1 | op2; break;
     case EOR: result = op1 ^ op2; break;
     default:
       UNIMPLEMENTED();
   }
 
   if (update_flags) {
-    nzcv().SetN(CalcNFlag(result, reg_size));
+    nzcv().SetN(CalcNFlag(result));
     nzcv().SetZ(CalcZFlag(result));
     nzcv().SetC(0);
     nzcv().SetV(0);
   }
 
-  set_reg(reg_size, instr->Rd(), result, instr->RdMode());
+  set_reg<T>(instr->Rd(), result, instr->RdMode());
 }
 
 
 void Simulator::VisitConditionalCompareRegister(Instruction* instr) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
-                                             : kWRegSizeInBits;
-  ConditionalCompareHelper(instr, reg(reg_size, instr->Rm()));
+  if (instr->SixtyFourBits()) {
+    ConditionalCompareHelper(instr, xreg(instr->Rm()));
+  } else {
+    ConditionalCompareHelper(instr, wreg(instr->Rm()));
+  }
 }
 
 
 void Simulator::VisitConditionalCompareImmediate(Instruction* instr) {
-  ConditionalCompareHelper(instr, instr->ImmCondCmp());
+  if (instr->SixtyFourBits()) {
+    ConditionalCompareHelper<int64_t>(instr, instr->ImmCondCmp());
+  } else {
+    ConditionalCompareHelper<int32_t>(instr, instr->ImmCondCmp());
+  }
 }
 
 
-void Simulator::ConditionalCompareHelper(Instruction* instr, int64_t op2) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
-                                             : kWRegSizeInBits;
-  int64_t op1 = reg(reg_size, instr->Rn());
+template<typename T>
+void Simulator::ConditionalCompareHelper(Instruction* instr, T op2) {
+  T op1 = reg<T>(instr->Rn());
 
   if (ConditionPassed(static_cast<Condition>(instr->Condition()))) {
     // If the condition passes, set the status flags to the result of comparing
     // the operands.
     if (instr->Mask(ConditionalCompareMask) == CCMP) {
-      AddWithCarry(reg_size, true, op1, ~op2, 1);
+      AddWithCarry<T>(true, op1, ~op2, 1);
     } else {
       ASSERT(instr->Mask(ConditionalCompareMask) == CCMN);
-      AddWithCarry(reg_size, true, op1, op2, 0);
+      AddWithCarry<T>(true, op1, op2, 0);
     }
   } else {
     // If the condition fails, set the status flags to the nzcv immediate.
     nzcv().SetFlags(instr->Nzcv());
   }
 }
 
 
 void Simulator::VisitLoadStoreUnsignedOffset(Instruction* instr) {
   int offset = instr->ImmLSUnsigned() << instr->SizeLS();
@@ skipping 14 matching lines @@
 void Simulator::VisitLoadStorePostIndex(Instruction* instr) {
   LoadStoreHelper(instr, instr->ImmLS(), PostIndex);
 }
 
 
 void Simulator::VisitLoadStoreRegisterOffset(Instruction* instr) {
   Extend ext = static_cast<Extend>(instr->ExtendMode());
   ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
   unsigned shift_amount = instr->ImmShiftLS() * instr->SizeLS();
 
-  int64_t offset = ExtendValue(kXRegSizeInBits, xreg(instr->Rm()), ext,
-                               shift_amount);
+  int64_t offset = ExtendValue(xreg(instr->Rm()), ext, shift_amount);
   LoadStoreHelper(instr, offset, Offset);
 }
 
 
 void Simulator::LoadStoreHelper(Instruction* instr,
                                 int64_t offset,
                                 AddrMode addrmode) {
   unsigned srcdst = instr->Rt();
   unsigned addr_reg = instr->Rn();
   uint8_t* address = LoadStoreAddress(addr_reg, offset, addrmode);
@@ skipping 19 matching lines @@
   switch (op) {
     case LDRB_w:
     case LDRH_w:
     case LDR_w:
     case LDR_x: set_xreg(srcdst, MemoryRead(address, num_bytes)); break;
     case STRB_w:
     case STRH_w:
     case STR_w:
     case STR_x: MemoryWrite(address, xreg(srcdst), num_bytes); break;
     case LDRSB_w: {
-      set_wreg(srcdst,
-               ExtendValue(kWRegSizeInBits, MemoryRead8(address), SXTB));
+      set_wreg(srcdst, ExtendValue<int32_t>(MemoryRead8(address), SXTB));
       break;
     }
     case LDRSB_x: {
-      set_xreg(srcdst,
-               ExtendValue(kXRegSizeInBits, MemoryRead8(address), SXTB));
+      set_xreg(srcdst, ExtendValue<int64_t>(MemoryRead8(address), SXTB));
       break;
     }
     case LDRSH_w: {
-      set_wreg(srcdst,
-               ExtendValue(kWRegSizeInBits, MemoryRead16(address), SXTH));
+      set_wreg(srcdst, ExtendValue<int32_t>(MemoryRead16(address), SXTH));
       break;
     }
     case LDRSH_x: {
-      set_xreg(srcdst,
-               ExtendValue(kXRegSizeInBits, MemoryRead16(address), SXTH));
+      set_xreg(srcdst, ExtendValue<int64_t>(MemoryRead16(address), SXTH));
       break;
     }
     case LDRSW_x: {
-      set_xreg(srcdst,
-               ExtendValue(kXRegSizeInBits, MemoryRead32(address), SXTW));
+      set_xreg(srcdst, ExtendValue<int64_t>(MemoryRead32(address), SXTW));
       break;
     }
     case LDR_s: set_sreg(srcdst, MemoryReadFP32(address)); break;
     case LDR_d: set_dreg(srcdst, MemoryReadFP64(address)); break;
     case STR_s: MemoryWriteFP32(address, sreg(srcdst)); break;
     case STR_d: MemoryWriteFP64(address, dreg(srcdst)); break;
     default: UNIMPLEMENTED();
   }
 
   // Handle the writeback for loads after the load to ensure safe pop
@@ skipping 79 matching lines @@
       set_xreg(rt, MemoryRead64(address));
       set_xreg(rt2, MemoryRead64(address + kXRegSize));
       break;
     }
     case LDP_d: {
       set_dreg(rt, MemoryReadFP64(address));
       set_dreg(rt2, MemoryReadFP64(address + kDRegSize));
       break;
     }
     case LDPSW_x: {
-      set_xreg(rt, ExtendValue(kXRegSizeInBits, MemoryRead32(address), SXTW));
-      set_xreg(rt2, ExtendValue(kXRegSizeInBits,
+      set_xreg(rt, ExtendValue<int64_t>(MemoryRead32(address), SXTW));
+      set_xreg(rt2, ExtendValue<int64_t>(
                MemoryRead32(address + kWRegSize), SXTW));
       break;
     }
     case STP_w: {
       MemoryWrite32(address, wreg(rt));
       MemoryWrite32(address + kWRegSize, wreg(rt2));
       break;
     }
     case STP_s: {
       MemoryWriteFP32(address, sreg(rt));
@@ skipping 195 matching lines @@
     default:
       UNREACHABLE();
   }
 
   // Update the destination register.
   set_xreg(instr->Rd(), new_xn_val);
 }
 
 
 void Simulator::VisitConditionalSelect(Instruction* instr) {
-  uint64_t new_val = xreg(instr->Rn());
-
   if (ConditionFailed(static_cast<Condition>(instr->Condition()))) {
-    new_val = xreg(instr->Rm());
+    uint64_t new_val = xreg(instr->Rm());
     switch (instr->Mask(ConditionalSelectMask)) {
-      case CSEL_w:
-      case CSEL_x: break;
-      case CSINC_w:
-      case CSINC_x: new_val++; break;
-      case CSINV_w:
-      case CSINV_x: new_val = ~new_val; break;
-      case CSNEG_w:
-      case CSNEG_x: new_val = -new_val; break;
+      case CSEL_w: set_wreg(instr->Rd(), new_val); break;
+      case CSEL_x: set_xreg(instr->Rd(), new_val); break;
+      case CSINC_w: set_wreg(instr->Rd(), new_val + 1); break;
+      case CSINC_x: set_xreg(instr->Rd(), new_val + 1); break;
+      case CSINV_w: set_wreg(instr->Rd(), ~new_val); break;
+      case CSINV_x: set_xreg(instr->Rd(), ~new_val); break;
+      case CSNEG_w: set_wreg(instr->Rd(), -new_val); break;
+      case CSNEG_x: set_xreg(instr->Rd(), -new_val); break;
       default: UNIMPLEMENTED();
     }
+  } else {
+    if (instr->SixtyFourBits()) {
+      set_xreg(instr->Rd(), xreg(instr->Rn()));
+    } else {
+      set_wreg(instr->Rd(), wreg(instr->Rn()));
+    }
   }
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
-                                             : kWRegSizeInBits;
-  set_reg(reg_size, instr->Rd(), new_val);
 }
 
 
 void Simulator::VisitDataProcessing1Source(Instruction* instr) {
   unsigned dst = instr->Rd();
   unsigned src = instr->Rn();
 
   switch (instr->Mask(DataProcessing1SourceMask)) {
     case RBIT_w: set_wreg(dst, ReverseBits(wreg(src), kWRegSizeInBits)); break;
     case RBIT_x: set_xreg(dst, ReverseBits(xreg(src), kXRegSizeInBits)); break;
@@ skipping 50 matching lines @@
                                                {0, 1, 2, 3, 4, 5, 6, 7} };
   uint64_t result = 0;
   for (int i = 0; i < 8; i++) {
     result <<= 8;
     result |= bytes[permute_table[mode][i]];
   }
   return result;
 }
 
 
-void Simulator::VisitDataProcessing2Source(Instruction* instr) {
+template <typename T>
+void Simulator::DataProcessing2Source(Instruction* instr) {
   Shift shift_op = NO_SHIFT;
-  int64_t result = 0;
+  T result = 0;
   switch (instr->Mask(DataProcessing2SourceMask)) {
-    case SDIV_w: {
-      int32_t rn = wreg(instr->Rn());
-      int32_t rm = wreg(instr->Rm());
-      if ((rn == kWMinInt) && (rm == -1)) {
-        result = kWMinInt;
+    case SDIV_w:
+    case SDIV_x: {
+      T rn = reg<T>(instr->Rn());
+      T rm = reg<T>(instr->Rm());
+      if ((rn == std::numeric_limits<T>::min()) && (rm == -1)) {
+        result = std::numeric_limits<T>::min();
       } else if (rm == 0) {
         // Division by zero can be trapped, but not on A-class processors.
         result = 0;
-      } else {
-        result = rn / rm;
-      }
-      break;
-    }
-    case SDIV_x: {
-      int64_t rn = xreg(instr->Rn());
-      int64_t rm = xreg(instr->Rm());
-      if ((rn == kXMinInt) && (rm == -1)) {
-        result = kXMinInt;
-      } else if (rm == 0) {
-        // Division by zero can be trapped, but not on A-class processors.
-        result = 0;
       } else {
         result = rn / rm;
       }
       break;
     }
-    case UDIV_w: {
-      uint32_t rn = static_cast<uint32_t>(wreg(instr->Rn()));
-      uint32_t rm = static_cast<uint32_t>(wreg(instr->Rm()));
+    case UDIV_w:
+    case UDIV_x: {
+      typedef typename make_unsigned<T>::type unsignedT;
+      unsignedT rn = static_cast<unsignedT>(reg<T>(instr->Rn()));
+      unsignedT rm = static_cast<unsignedT>(reg<T>(instr->Rm()));
       if (rm == 0) {
         // Division by zero can be trapped, but not on A-class processors.
         result = 0;
-      } else {
-        result = rn / rm;
-      }
-      break;
-    }
-    case UDIV_x: {
-      uint64_t rn = static_cast<uint64_t>(xreg(instr->Rn()));
-      uint64_t rm = static_cast<uint64_t>(xreg(instr->Rm()));
-      if (rm == 0) {
-        // Division by zero can be trapped, but not on A-class processors.
-        result = 0;
       } else {
         result = rn / rm;
       }
       break;
     }
     case LSLV_w:
     case LSLV_x: shift_op = LSL; break;
     case LSRV_w:
     case LSRV_x: shift_op = LSR; break;
     case ASRV_w:
     case ASRV_x: shift_op = ASR; break;
     case RORV_w:
     case RORV_x: shift_op = ROR; break;
     default: UNIMPLEMENTED();
   }
 
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
-                                             : kWRegSizeInBits;
   if (shift_op != NO_SHIFT) {
     // Shift distance encoded in the least-significant five/six bits of the
     // register.
-    int mask = (instr->SixtyFourBits() == 1) ? kShiftAmountXRegMask
-                                             : kShiftAmountWRegMask;
-    unsigned shift = wreg(instr->Rm()) & mask;
-    result = ShiftOperand(reg_size, reg(reg_size, instr->Rn()), shift_op,
-                          shift);
+    unsigned shift = wreg(instr->Rm());
+    if (sizeof(T) == kWRegSize) {
+      shift &= kShiftAmountWRegMask;
+    } else {
+      shift &= kShiftAmountXRegMask;
+    }
+    result = ShiftOperand(reg<T>(instr->Rn()), shift_op, shift);
   }
-  set_reg(reg_size, instr->Rd(), result);
+  set_reg<T>(instr->Rd(), result);
 }
 
 
+void Simulator::VisitDataProcessing2Source(Instruction* instr) {
+  if (instr->SixtyFourBits()) {
+    DataProcessing2Source<int64_t>(instr);
+  } else {
+    DataProcessing2Source<int32_t>(instr);
+  }
+}
+
+
 // The algorithm used is described in section 8.2 of
 //   Hacker's Delight, by Henry S. Warren, Jr.
 // It assumes that a right shift on a signed integer is an arithmetic shift.
 static int64_t MultiplyHighSigned(int64_t u, int64_t v) {
   uint64_t u0, v0, w0;
   int64_t u1, v1, w1, w2, t;
 
   u0 = u & 0xffffffffL;
   u1 = u >> 32;
   v0 = v & 0xffffffffL;
   v1 = v >> 32;
 
   w0 = u0 * v0;
   t = u1 * v0 + (w0 >> 32);
   w1 = t & 0xffffffffL;
   w2 = t >> 32;
   w1 = u0 * v1 + w1;
 
   return u1 * v1 + w2 + (w1 >> 32);
 }
 
 
 void Simulator::VisitDataProcessing3Source(Instruction* instr) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
-                                             : kWRegSizeInBits;
-
   int64_t result = 0;
   // Extract and sign- or zero-extend 32-bit arguments for widening operations.
   uint64_t rn_u32 = reg<uint32_t>(instr->Rn());
   uint64_t rm_u32 = reg<uint32_t>(instr->Rm());
   int64_t rn_s32 = reg<int32_t>(instr->Rn());
   int64_t rm_s32 = reg<int32_t>(instr->Rm());
   switch (instr->Mask(DataProcessing3SourceMask)) {
     case MADD_w:
     case MADD_x:
       result = xreg(instr->Ra()) + (xreg(instr->Rn()) * xreg(instr->Rm()));
       break;
     case MSUB_w:
     case MSUB_x:
       result = xreg(instr->Ra()) - (xreg(instr->Rn()) * xreg(instr->Rm()));
       break;
     case SMADDL_x: result = xreg(instr->Ra()) + (rn_s32 * rm_s32); break;
     case SMSUBL_x: result = xreg(instr->Ra()) - (rn_s32 * rm_s32); break;
     case UMADDL_x: result = xreg(instr->Ra()) + (rn_u32 * rm_u32); break;
     case UMSUBL_x: result = xreg(instr->Ra()) - (rn_u32 * rm_u32); break;
     case SMULH_x:
       ASSERT(instr->Ra() == kZeroRegCode);
       result = MultiplyHighSigned(xreg(instr->Rn()), xreg(instr->Rm()));
       break;
     default: UNIMPLEMENTED();
   }
-  set_reg(reg_size, instr->Rd(), result);
+
+  if (instr->SixtyFourBits()) {
+    set_xreg(instr->Rd(), result);
+  } else {
+    set_wreg(instr->Rd(), result);
+  }
 }
 
 
-void Simulator::VisitBitfield(Instruction* instr) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
-                                             : kWRegSizeInBits;
-  int64_t reg_mask = instr->SixtyFourBits() ? kXRegMask : kWRegMask;
-  int64_t R = instr->ImmR();
-  int64_t S = instr->ImmS();
-  int64_t diff = S - R;
-  int64_t mask;
+template <typename T>
+void Simulator::BitfieldHelper(Instruction* instr) {
+  typedef typename make_unsigned<T>::type unsignedT;
+  T reg_size = sizeof(T) * 8;
+  T R = instr->ImmR();
+  T S = instr->ImmS();
+  T diff = S - R;
+  T mask;
   if (diff >= 0) {
-    mask = diff < reg_size - 1 ? (1L << (diff + 1)) - 1
-                               : reg_mask;
+    mask = diff < reg_size - 1 ? (static_cast<T>(1) << (diff + 1)) - 1
+                               : static_cast<T>(-1);
   } else {
     mask = ((1L << (S + 1)) - 1);
     mask = (static_cast<uint64_t>(mask) >> R) | (mask << (reg_size - R));
     diff += reg_size;
   }
 
   // inzero indicates if the extracted bitfield is inserted into the
   // destination register value or in zero.
   // If extend is true, extend the sign of the extracted bitfield.
   bool inzero = false;
   bool extend = false;
   switch (instr->Mask(BitfieldMask)) {
     case BFM_x:
     case BFM_w:
       break;
     case SBFM_x:
     case SBFM_w:
       inzero = true;
       extend = true;
       break;
     case UBFM_x:
     case UBFM_w:
       inzero = true;
       break;
     default:
       UNIMPLEMENTED();
   }
 
-  int64_t dst = inzero ? 0 : reg(reg_size, instr->Rd());
-  int64_t src = reg(reg_size, instr->Rn());
+  T dst = inzero ? 0 : reg<T>(instr->Rd());
+  T src = reg<T>(instr->Rn());
   // Rotate source bitfield into place.
-  int64_t result = (static_cast<uint64_t>(src) >> R) | (src << (reg_size - R));
+  T result = (static_cast<unsignedT>(src) >> R) | (src << (reg_size - R));
   // Determine the sign extension.
-  int64_t topbits_preshift = (1L << (reg_size - diff - 1)) - 1;
-  int64_t signbits = (extend && ((src >> S) & 1) ? topbits_preshift : 0)
-                     << (diff + 1);
+  T topbits_preshift = (static_cast<T>(1) << (reg_size - diff - 1)) - 1;
+  T signbits = (extend && ((src >> S) & 1) ? topbits_preshift : 0)
+               << (diff + 1);
 
   // Merge sign extension, dest/zero and bitfield.
   result = signbits | (result & mask) | (dst & ~mask);
 
-  set_reg(reg_size, instr->Rd(), result);
+  set_reg<T>(instr->Rd(), result);
+}
+
+
+void Simulator::VisitBitfield(Instruction* instr) {
+  if (instr->SixtyFourBits()) {
+    BitfieldHelper<int64_t>(instr);
+  } else {
+    BitfieldHelper<int32_t>(instr);
+  }
 }
 
 
 void Simulator::VisitExtract(Instruction* instr) {
-  unsigned lsb = instr->ImmS();
-  unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits
-                                                    : kWRegSizeInBits;
-  set_reg(reg_size,
-          instr->Rd(),
-          (static_cast<uint64_t>(reg(reg_size, instr->Rm())) >> lsb) |
-          (reg(reg_size, instr->Rn()) << (reg_size - lsb)));
+  if (instr->SixtyFourBits()) {
+    Extract<uint64_t>(instr);
+  } else {
+    Extract<uint32_t>(instr);
+  }
 }
 
 
 void Simulator::VisitFPImmediate(Instruction* instr) {
   AssertSupportedFPCR();
 
   unsigned dest = instr->Rd();
   switch (instr->Mask(FPImmediateMask)) {
     case FMOV_s_imm: set_sreg(dest, instr->ImmFP32()); break;
     case FMOV_d_imm: set_dreg(dest, instr->ImmFP64()); break;
@@ skipping 1604 matching lines @@
 
   delete[] format;
 }
 
 
 #endif  // USE_SIMULATOR
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM64