PPC/s390: [turbofan]: Support using push instructions for setting up tail call parameters

PPC/s390: [turbofan]: Support using push instructions for setting up tail call parameters

Port bd0d9e7d87d418b0c6a84f298e27058645083dad

Original commit message:

    This optimizes the passing of stack parameters in function calls.

    For some architectures (ia32/x64), using pushes when possible instead
    of bumping the stack and then storing parameters generates much
    smaller code, and in some cases is faster (e.g. when a push of a memory
    location can implement a memory-to-memory copy and thus elide an
    intermediate load. On others (e.g. ARM), the benefit is smaller, where
    it's only possible to elide direct stack pointer adjustment in certain cases
    or combine multiple register stores into a single instruction in other limited
    situations. On yet other platforms (ARM64, MIPS), there are no push instructions,
    and this optimization isn't used at all.

    Ideally, this mechanism would be used for both tail calls and normal calls,
    but "normal" calls are currently pretty efficient, and tail calls are very
    inefficient, so this CL sets the bar low for building a new mechanism to
    handle parameter pushing that only needs to raise the bar on tail calls for now.

    The key aspect of this change is that adjustment to the stack pointer
    for tail calls (and perhaps later real calls) is an explicit step separate from
    instruction selection and gap resolution, but aware of both, making it possible
    to safely recognize gap moves that are actually pushes.

R=danno@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com, mbrandy@us.ibm.com

BUG=
LOG=N

Committed: https://crrev.com/433572b8e069db722642e7159328ea94cad1705c
Cr-Commit-Position: refs/heads/master@{#37561}

[JaideepBajwa, 2016-07-06 15:44:47]

PTAL

[john.yan, 2016-07-06 15:46:03]

lgtm

[JaideepBajwa, 2016-07-06 16:58:02]

The CQ bit was checked by bjaideep@ca.ibm.com

[commit-bot: I haz the power, 2016-07-06 16:58:08]

CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2016-07-06 17:20:40]

Committed patchset #1 (id:1)

[commit-bot: I haz the power, 2016-07-06 17:21:17]

Description was changed from

==========
PPC/s390: [turbofan]: Support using push instructions for setting up tail call
parameters

Port bd0d9e7d87d418b0c6a84f298e27058645083dad

Original commit message:

    This optimizes the passing of stack parameters in function calls.

    For some architectures (ia32/x64), using pushes when possible instead
    of bumping the stack and then storing parameters generates much
    smaller code, and in some cases is faster (e.g. when a push of a memory
    location can implement a memory-to-memory copy and thus elide an
    intermediate load. On others (e.g. ARM), the benefit is smaller, where
    it's only possible to elide direct stack pointer adjustment in certain cases
    or combine multiple register stores into a single instruction in other
limited
    situations. On yet other platforms (ARM64, MIPS), there are no push
instructions,
    and this optimization isn't used at all.

    Ideally, this mechanism would be used for both tail calls and normal calls,
    but "normal" calls are currently pretty efficient, and tail calls are very
    inefficient, so this CL sets the bar low for building a new mechanism to
    handle parameter pushing that only needs to raise the bar on tail calls for
now.

    The key aspect of this change is that adjustment to the stack pointer
    for tail calls (and perhaps later real calls) is an explicit step separate
from
    instruction selection and gap resolution, but aware of both, making it
possible
    to safely recognize gap moves that are actually pushes.

R=danno@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com,
michael_dawson@ca.ibm.com, mbrandy@us.ibm.com

BUG=
LOG=N
==========

to

==========
PPC/s390: [turbofan]: Support using push instructions for setting up tail call
parameters

Port bd0d9e7d87d418b0c6a84f298e27058645083dad

Original commit message:

    This optimizes the passing of stack parameters in function calls.

    For some architectures (ia32/x64), using pushes when possible instead
    of bumping the stack and then storing parameters generates much
    smaller code, and in some cases is faster (e.g. when a push of a memory
    location can implement a memory-to-memory copy and thus elide an
    intermediate load. On others (e.g. ARM), the benefit is smaller, where
    it's only possible to elide direct stack pointer adjustment in certain cases
    or combine multiple register stores into a single instruction in other
limited
    situations. On yet other platforms (ARM64, MIPS), there are no push
instructions,
    and this optimization isn't used at all.

    Ideally, this mechanism would be used for both tail calls and normal calls,
    but "normal" calls are currently pretty efficient, and tail calls are very
    inefficient, so this CL sets the bar low for building a new mechanism to
    handle parameter pushing that only needs to raise the bar on tail calls for
now.

    The key aspect of this change is that adjustment to the stack pointer
    for tail calls (and perhaps later real calls) is an explicit step separate
from
    instruction selection and gap resolution, but aware of both, making it
possible
    to safely recognize gap moves that are actually pushes.

R=danno@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com,
michael_dawson@ca.ibm.com, mbrandy@us.ibm.com

BUG=
LOG=N

Committed: https://crrev.com/433572b8e069db722642e7159328ea94cad1705c
Cr-Commit-Position: refs/heads/master@{#37561}
==========

[commit-bot: I haz the power, 2016-07-06 17:21:18]

Patchset 1 (id:??) landed as
https://crrev.com/433572b8e069db722642e7159328ea94cad1705c
Cr-Commit-Position: refs/heads/master@{#37561}