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Side by Side Diff: src/compiler/mips64/instruction-codes-mips64.h

Issue 2122853002: Implement UnaligedLoad and UnaligedStore turbofan operators. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 5 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 98 matching lines...) Expand 10 before | Expand all | Expand 10 after
109 V(Mips64CvtSW) \ 109 V(Mips64CvtSW) \
110 V(Mips64CvtSUw) \ 110 V(Mips64CvtSUw) \
111 V(Mips64CvtSUl) \ 111 V(Mips64CvtSUl) \
112 V(Mips64CvtDL) \ 112 V(Mips64CvtDL) \
113 V(Mips64CvtDUw) \ 113 V(Mips64CvtDUw) \
114 V(Mips64CvtDUl) \ 114 V(Mips64CvtDUl) \
115 V(Mips64Lb) \ 115 V(Mips64Lb) \
116 V(Mips64Lbu) \ 116 V(Mips64Lbu) \
117 V(Mips64Sb) \ 117 V(Mips64Sb) \
118 V(Mips64Lh) \ 118 V(Mips64Lh) \
119 V(Mips64Ulh) \
119 V(Mips64Lhu) \ 120 V(Mips64Lhu) \
121 V(Mips64Ulhu) \
120 V(Mips64Sh) \ 122 V(Mips64Sh) \
123 V(Mips64Ush) \
124 V(Mips64Ld) \
125 V(Mips64Uld) \
121 V(Mips64Lw) \ 126 V(Mips64Lw) \
127 V(Mips64Ulw) \
122 V(Mips64Lwu) \ 128 V(Mips64Lwu) \
129 V(Mips64Ulwu) \
123 V(Mips64Sw) \ 130 V(Mips64Sw) \
124 V(Mips64Ld) \ 131 V(Mips64Usw) \
125 V(Mips64Sd) \ 132 V(Mips64Sd) \
133 V(Mips64Usd) \
126 V(Mips64Lwc1) \ 134 V(Mips64Lwc1) \
135 V(Mips64Ulwc1) \
127 V(Mips64Swc1) \ 136 V(Mips64Swc1) \
137 V(Mips64Uswc1) \
128 V(Mips64Ldc1) \ 138 V(Mips64Ldc1) \
139 V(Mips64Uldc1) \
129 V(Mips64Sdc1) \ 140 V(Mips64Sdc1) \
141 V(Mips64Usdc1) \
130 V(Mips64BitcastDL) \ 142 V(Mips64BitcastDL) \
131 V(Mips64BitcastLD) \ 143 V(Mips64BitcastLD) \
132 V(Mips64Float64ExtractLowWord32) \ 144 V(Mips64Float64ExtractLowWord32) \
133 V(Mips64Float64ExtractHighWord32) \ 145 V(Mips64Float64ExtractHighWord32) \
134 V(Mips64Float64InsertLowWord32) \ 146 V(Mips64Float64InsertLowWord32) \
135 V(Mips64Float64InsertHighWord32) \ 147 V(Mips64Float64InsertHighWord32) \
136 V(Mips64Float64Max) \ 148 V(Mips64Float64Max) \
137 V(Mips64Float64Min) \ 149 V(Mips64Float64Min) \
138 V(Mips64Float64SilenceNaN) \ 150 V(Mips64Float64SilenceNaN) \
139 V(Mips64Float32Max) \ 151 V(Mips64Float32Max) \
(...skipping 19 matching lines...) Expand all
159 #define TARGET_ADDRESSING_MODE_LIST(V) \ 171 #define TARGET_ADDRESSING_MODE_LIST(V) \
160 V(MRI) /* [%r0 + K] */ \ 172 V(MRI) /* [%r0 + K] */ \
161 V(MRR) /* [%r0 + %r1] */ 173 V(MRR) /* [%r0 + %r1] */
162 174
163 175
164 } // namespace compiler 176 } // namespace compiler
165 } // namespace internal 177 } // namespace internal
166 } // namespace v8 178 } // namespace v8
167 179
168 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 180 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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