Subzero, MIPS32: Extend InstMIPS32Mov to support different data types

tests_lit/llvm2ice_tests/int-arg.ll

 ; This file checks that Subzero generates code in accordance with the
 ; calling convention for integers.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented)
 ; once enough infrastructure is in. Also, switch to --filetype=obj
 ; when possible.
@@ skipping 24 matching lines @@
 define internal i32 @test_returning32_arg0(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) {
 entry:
   ret i32 %arg0
 }
 ; CHECK-LABEL: test_returning32_arg0
 ; CHECK-NEXT: mov eax,{{.*}} [esp+0x4]
 ; CHECK-NEXT: ret
 ; ARM32-LABEL: test_returning32_arg0
 ; ARM32-NEXT: bx lr
 ; MIPS32-LABEL: test_returning32_arg0
-; MIPS32: move  v0,a0
+; MIPS32: add v0,zero,a0
 ; MIPS32-NEXT: jr       ra
 
 define internal i32 @test_returning32_arg1(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) {
 entry:
   ret i32 %arg1
 }
 ; CHECK-LABEL: test_returning32_arg1
 ; CHECK-NEXT: mov eax,{{.*}} [esp+0x8]
 ; CHECK-NEXT: ret
 ; ARM32-LABEL: test_returning32_arg1
 ; ARM32-NEXT: mov r0, r1
 ; ARM32-NEXT: bx lr
 ; MIPS32-LABEL: test_returning32_arg1
-; MIPS32: move  v0,a1
+; MIPS32: add v0,zero,a1
 ; MIPS32-NEXT: jr       ra
 
 define internal i32 @test_returning32_arg2(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) {
 entry:
   ret i32 %arg2
 }
 ; CHECK-LABEL: test_returning32_arg2
 ; CHECK-NEXT: mov eax,{{.*}} [esp+0xc]
 ; CHECK-NEXT: ret
 ; ARM32-LABEL: test_returning32_arg2
 ; ARM32-NEXT: mov r0, r2
 ; ARM32-NEXT: bx lr
 ; MIPS32-LABEL: test_returning32_arg2
-; MIPS32: move  v0,a2
+; MIPS32: add v0,zero,a2
 ; MIPS32-NEXT: jr       ra
 
 
 define internal i32 @test_returning32_arg3(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) {
 entry:
   ret i32 %arg3
 }
 ; CHECK-LABEL: test_returning32_arg3
 ; CHECK-NEXT: mov eax,{{.*}} [esp+0x10]
 ; CHECK-NEXT: ret
@@ skipping 31 matching lines @@
 entry:
   ret i64 %arg0
 }
 ; CHECK-LABEL: test_returning64_arg0
 ; CHECK-NEXT: mov {{.*}} [esp+0x4]
 ; CHECK-NEXT: mov {{.*}} [esp+0x8]
 ; CHECK: ret
 ; ARM32-LABEL: test_returning64_arg0
 ; ARM32-NEXT: bx lr
 ; MIPS32-LABEL: test_returning64_arg0
-; MIPS32-NEXT: move     v0,a0
-; MIPS32-NEXT: move     v1,a1
+; MIPS32-NEXT: add v0,zero,a0
+; MIPS32-NEXT: add v1,zero,a1
 
 
 define internal i64 @test_returning64_arg1(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) {
 entry:
   ret i64 %arg1
 }
 ; CHECK-LABEL: test_returning64_arg1
 ; CHECK-NEXT: mov {{.*}} [esp+0xc]
 ; CHECK-NEXT: mov {{.*}} [esp+0x10]
 ; CHECK: ret
 ; ARM32-LABEL: test_returning64_arg1
 ; ARM32-NEXT: mov r0, r2
 ; ARM32-NEXT: mov r1, r3
 ; ARM32-NEXT: bx lr
 ; MIPS32-LABEL: test_returning64_arg1
-; MIPS32-NEXT: move     v0,a2
-; MIPS32-NEXT: move     v1,a3
+; MIPS32-NEXT: add v0,zero,a2
+; MIPS32-NEXT: add v1,zero,a3
 
 define internal i64 @test_returning64_arg2(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) {
 entry:
   ret i64 %arg2
 }
 ; CHECK-LABEL: test_returning64_arg2
 ; CHECK-NEXT: mov {{.*}} [esp+0x14]
 ; CHECK-NEXT: mov {{.*}} [esp+0x18]
 ; CHECK: ret
 ; ARM32-LABEL: test_returning64_arg2
@@ skipping 139 matching lines @@
 ; ARM32-DAG: mov [[REG1:.*]], r1
 ; ARM32-DAG: mov [[REG2:.*]], r2
 ; ARM32-DAG: mov [[REG3:.*]], r3
 ; ARM32: str [[REG2]], [sp]
 ; ARM32: str [[REG1]], [sp, #4]
 ; ARM32-DAG: mov r0
 ; ARM32-DAG: mov r1
 ; ARM32-DAG: mov r2
 ; ARM32-DAG: mov r3, [[REG3]]
 ; ARM32: bl