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|    1 // Copyright (c) 2016, the Dart project authors.  Please see the AUTHORS file |    1 // Copyright (c) 2016, the Dart project authors.  Please see the AUTHORS file | 
|    2 // for details. All rights reserved. Use of this source code is governed by a |    2 // for details. All rights reserved. Use of this source code is governed by a | 
|    3 // BSD-style license that can be found in the LICENSE file. |    3 // BSD-style license that can be found in the LICENSE file. | 
|    4  |    4  | 
|    5 #ifndef VM_CONSTANTS_DBC_H_ |    5 #ifndef VM_CONSTANTS_DBC_H_ | 
|    6 #define VM_CONSTANTS_DBC_H_ |    6 #define VM_CONSTANTS_DBC_H_ | 
|    7  |    7  | 
|    8 #include "platform/globals.h" |    8 #include "platform/globals.h" | 
|    9 #include "platform/assert.h" |    9 #include "platform/assert.h" | 
|   10 #include "platform/utils.h" |   10 #include "platform/utils.h" | 
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|  176 //    instruction (which implements a slow path fallback). |  176 //    instruction (which implements a slow path fallback). | 
|  177 // |  177 // | 
|  178 //  - Add, Sub, Mul, Div, Mod, Shl, Shr rA, rB, rC |  178 //  - Add, Sub, Mul, Div, Mod, Shl, Shr rA, rB, rC | 
|  179 // |  179 // | 
|  180 //    Arithmetic operations on Smis. FP[rA] <- FP[rB] op FP[rC]. |  180 //    Arithmetic operations on Smis. FP[rA] <- FP[rB] op FP[rC]. | 
|  181 //    If these instructions can trigger a deoptimization, the following |  181 //    If these instructions can trigger a deoptimization, the following | 
|  182 //    instruction should be Deopt. If no deoptimization should be triggered, |  182 //    instruction should be Deopt. If no deoptimization should be triggered, | 
|  183 //    the immediately following instruction is skipped. These instructions |  183 //    the immediately following instruction is skipped. These instructions | 
|  184 //    expect their operands to be Smis, but don't check that they are. |  184 //    expect their operands to be Smis, but don't check that they are. | 
|  185 // |  185 // | 
 |  186 //  - DAdd, DSub, DMul, DDiv rA, rB, rC | 
 |  187 // | 
 |  188 //    Arithmetic operaions on unboxed doubles. FP[rA] <- FP[rB] op FP[rC]. | 
 |  189 // | 
|  186 //  - Neg rA , rD |  190 //  - Neg rA , rD | 
|  187 // |  191 // | 
|  188 //    FP[rA] <- -FP[rD]. Assumes FP[rD] is a Smi. If there is no overflow the |  192 //    FP[rA] <- -FP[rD]. Assumes FP[rD] is a Smi. If there is no overflow the | 
|  189 //    immediately following instruction is skipped. |  193 //    immediately following instruction is skipped. | 
|  190 // |  194 // | 
 |  195 //  - DNeg rA, rD | 
 |  196 // | 
 |  197 //    FP[rA] <- -FP[rD]. Assumes FP[rD] is an unboxed double. | 
 |  198 // | 
|  191 //  - BitOr, BitAnd, BitXor rA, rB, rC |  199 //  - BitOr, BitAnd, BitXor rA, rB, rC | 
|  192 // |  200 // | 
|  193 //    FP[rA] <- FP[rB] op FP[rC]. These instructions expect their operands to be |  201 //    FP[rA] <- FP[rB] op FP[rC]. These instructions expect their operands to be | 
|  194 //    Smis, but don't check that they are. |  202 //    Smis, but don't check that they are. | 
|  195 // |  203 // | 
|  196 //  - BitNot rA, rD |  204 //  - BitNot rA, rD | 
|  197 // |  205 // | 
|  198 //    FP[rA] <- ~FP[rD]. As above, assumes FP[rD] is a Smi. |  206 //    FP[rA] <- ~FP[rD]. As above, assumes FP[rD] is a Smi. | 
|  199 // |  207 // | 
 |  208 //  - WriteIntoDouble rA, rD | 
 |  209 // | 
 |  210 //    Box the double in FP[rD] with the result in FP[rA]. | 
 |  211 // | 
 |  212 //  - UnboxDouble rA, rD | 
 |  213 // | 
 |  214 //    Unbox the double in FP[rD] into FP[rA]. Assumes FP[rD] is a double. | 
 |  215 // | 
 |  216 //  - CheckedUnboxDouble rA, rD | 
 |  217 // | 
 |  218 //    Unboxes FP[rD] into FP[rA] and skips the following instruction unless | 
 |  219 //    FP[rD] is not a double or a Smi. When FP[rD] is a Smi, converts it to a | 
 |  220 //    double. | 
 |  221 // | 
 |  222 //  - SmiToDouble rA, rD | 
 |  223 // | 
 |  224 //    Convert the Smi in FP[rD] to an unboxed double in FP[rA]. | 
 |  225 // | 
|  200 //  - StoreStaticT`OS D |  226 //  - StoreStaticT`OS D | 
|  201 // |  227 // | 
|  202 //    Stores TOS into the static field PP[D]. |  228 //    Stores TOS into the static field PP[D]. | 
|  203 // |  229 // | 
|  204 //  - PushStatic |  230 //  - PushStatic | 
|  205 // |  231 // | 
|  206 //    Pushes value of the static field PP[D] on to the stack. |  232 //    Pushes value of the static field PP[D] on to the stack. | 
|  207 // |  233 // | 
|  208 //  - InitStaticTOS |  234 //  - InitStaticTOS | 
|  209 // |  235 // | 
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|  223 //        IfNeStrictTOS |  249 //        IfNeStrictTOS | 
|  224 //        Jump T         ;; jump if not equal |  250 //        Jump T         ;; jump if not equal | 
|  225 // |  251 // | 
|  226 //  - If<Cond>Null rA |  252 //  - If<Cond>Null rA | 
|  227 // |  253 // | 
|  228 //    Cond is Eq or Ne. Skips the next instruction unless the given condition |  254 //    Cond is Eq or Ne. Skips the next instruction unless the given condition | 
|  229 //    holds. |  255 //    holds. | 
|  230 // |  256 // | 
|  231 //  - If<Cond> rA, rD |  257 //  - If<Cond> rA, rD | 
|  232 // |  258 // | 
|  233 //    Cond is Le, Lt, Ge, Gt, or unsigned variants ULe, ULt, UGe, UGt. |  259 //    Cond is Le, Lt, Ge, Gt, unsigned variants ULe, ULt, UGe, UGt, and | 
 |  260 //    unboxed double variants DEq, DNe, DLe, DLt, DGe, DGt. | 
|  234 //    Skips the next instruction unless FP[rA] <Cond> FP[rD]. Assumes that |  261 //    Skips the next instruction unless FP[rA] <Cond> FP[rD]. Assumes that | 
|  235 //    FP[rA] and FP[rD] are Smis. |  262 //    FP[rA] and FP[rD] are Smis or unboxed doubles as inidcated by <Cond>. | 
|  236 // |  263 // | 
|  237 //  - CreateArrayTOS |  264 //  - CreateArrayTOS | 
|  238 // |  265 // | 
|  239 //    Allocate array of length SP[0] with type arguments SP[-1]. |  266 //    Allocate array of length SP[0] with type arguments SP[-1]. | 
|  240 // |  267 // | 
|  241 //  - Allocate D |  268 //  - Allocate D | 
|  242 // |  269 // | 
|  243 //    Allocate object of class PP[D] with no type arguments. |  270 //    Allocate object of class PP[D] with no type arguments. | 
|  244 // |  271 // | 
|  245 //  - AllocateT |  272 //  - AllocateT | 
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|  391 // |  418 // | 
|  392 //    The next D instructions must be Nops whose D field encodes a class id. If |  419 //    The next D instructions must be Nops whose D field encodes a class id. If | 
|  393 //    the class id of FP[rA] matches, jump to PC + N + 1 if the matching Nop's |  420 //    the class id of FP[rA] matches, jump to PC + N + 1 if the matching Nop's | 
|  394 //    A != 0 or PC + N + 2 if the matching Nop's A = 0. If no match is found, |  421 //    A != 0 or PC + N + 2 if the matching Nop's A = 0. If no match is found, | 
|  395 //    jump to PC + N. |  422 //    jump to PC + N. | 
|  396 // |  423 // | 
|  397 //  - CheckSmi rA |  424 //  - CheckSmi rA | 
|  398 // |  425 // | 
|  399 //    If FP[rA] is a Smi, then skip the next instruction. |  426 //    If FP[rA] is a Smi, then skip the next instruction. | 
|  400 // |  427 // | 
 |  428 //  - CheckEitherNonSmi rA, rD | 
 |  429 // | 
 |  430 //    If either FP[rA] or FP[rD] is not a Smi, then skip the next instruction. | 
 |  431 // | 
|  401 //  - CheckClassId rA, D |  432 //  - CheckClassId rA, D | 
|  402 // |  433 // | 
|  403 //    If the object at FP[rA]'s class id matches the class id D, then skip the |  434 //    If the class id in FP[rA] matches the class id D, then skip the | 
|  404 //    following instruction. |  435 //    following instruction. | 
|  405 // |  436 // | 
|  406 //  - CheckDenseSwitch rA, D |  437 //  - CheckDenseSwitch rA, D | 
|  407 // |  438 // | 
|  408 //    Skips the next 3 instructions if the object at FP[rA] is a valid class for |  439 //    Skips the next 3 instructions if the object at FP[rA] is a valid class for | 
|  409 //    a dense switch with low cid encoded in the following Nop instruction, and |  440 //    a dense switch with low cid encoded in the following Nop instruction, and | 
|  410 //    the cid mask encoded in the Nop instruction after that, or if D == 1 and |  441 //    the cid mask encoded in the Nop instruction after that, or if D == 1 and | 
|  411 //    FP[rA] is a Smi. Skips 2 instructions otherwise. |  442 //    FP[rA] is a Smi. Skips 2 instructions otherwise. | 
|  412 // |  443 // | 
|  413 //  - CheckCids rA, rB, rC |  444 //  - CheckCids rA, rB, rC | 
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|  519   V(Mul,                         A_B_C, reg, reg, reg) \ |  550   V(Mul,                         A_B_C, reg, reg, reg) \ | 
|  520   V(Div,                         A_B_C, reg, reg, reg) \ |  551   V(Div,                         A_B_C, reg, reg, reg) \ | 
|  521   V(Mod,                         A_B_C, reg, reg, reg) \ |  552   V(Mod,                         A_B_C, reg, reg, reg) \ | 
|  522   V(Shl,                         A_B_C, reg, reg, reg) \ |  553   V(Shl,                         A_B_C, reg, reg, reg) \ | 
|  523   V(Shr,                         A_B_C, reg, reg, reg) \ |  554   V(Shr,                         A_B_C, reg, reg, reg) \ | 
|  524   V(Neg,                           A_D, reg, reg, ___) \ |  555   V(Neg,                           A_D, reg, reg, ___) \ | 
|  525   V(BitOr,                       A_B_C, reg, reg, reg) \ |  556   V(BitOr,                       A_B_C, reg, reg, reg) \ | 
|  526   V(BitAnd,                      A_B_C, reg, reg, reg) \ |  557   V(BitAnd,                      A_B_C, reg, reg, reg) \ | 
|  527   V(BitXor,                      A_B_C, reg, reg, reg) \ |  558   V(BitXor,                      A_B_C, reg, reg, reg) \ | 
|  528   V(BitNot,                        A_D, reg, reg, ___) \ |  559   V(BitNot,                        A_D, reg, reg, ___) \ | 
 |  560   V(WriteIntoDouble,               A_D, reg, reg, ___) \ | 
 |  561   V(UnboxDouble,                   A_D, reg, reg, ___) \ | 
 |  562   V(CheckedUnboxDouble,            A_D, reg, reg, ___) \ | 
 |  563   V(SmiToDouble,                   A_D, reg, reg, ___) \ | 
 |  564   V(DAdd,                        A_B_C, reg, reg, reg) \ | 
 |  565   V(DSub,                        A_B_C, reg, reg, reg) \ | 
 |  566   V(DMul,                        A_B_C, reg, reg, reg) \ | 
 |  567   V(DDiv,                        A_B_C, reg, reg, reg) \ | 
 |  568   V(DNeg,                          A_D, reg, reg, ___) \ | 
|  529   V(StoreStaticTOS,                  D, lit, ___, ___) \ |  569   V(StoreStaticTOS,                  D, lit, ___, ___) \ | 
|  530   V(PushStatic,                      D, lit, ___, ___) \ |  570   V(PushStatic,                      D, lit, ___, ___) \ | 
|  531   V(InitStaticTOS,                   0, ___, ___, ___) \ |  571   V(InitStaticTOS,                   0, ___, ___, ___) \ | 
|  532   V(IfNeStrictTOS,                   0, ___, ___, ___) \ |  572   V(IfNeStrictTOS,                   0, ___, ___, ___) \ | 
|  533   V(IfEqStrictTOS,                   0, ___, ___, ___) \ |  573   V(IfEqStrictTOS,                   0, ___, ___, ___) \ | 
|  534   V(IfNeStrictNumTOS,                0, ___, ___, ___) \ |  574   V(IfNeStrictNumTOS,                0, ___, ___, ___) \ | 
|  535   V(IfEqStrictNumTOS,                0, ___, ___, ___) \ |  575   V(IfEqStrictNumTOS,                0, ___, ___, ___) \ | 
|  536   V(IfNeStrict,                    A_D, reg, reg, ___) \ |  576   V(IfNeStrict,                    A_D, reg, reg, ___) \ | 
|  537   V(IfEqStrict,                    A_D, reg, reg, ___) \ |  577   V(IfEqStrict,                    A_D, reg, reg, ___) \ | 
|  538   V(IfLe,                          A_D, reg, reg, ___) \ |  578   V(IfLe,                          A_D, reg, reg, ___) \ | 
|  539   V(IfLt,                          A_D, reg, reg, ___) \ |  579   V(IfLt,                          A_D, reg, reg, ___) \ | 
|  540   V(IfGe,                          A_D, reg, reg, ___) \ |  580   V(IfGe,                          A_D, reg, reg, ___) \ | 
|  541   V(IfGt,                          A_D, reg, reg, ___) \ |  581   V(IfGt,                          A_D, reg, reg, ___) \ | 
|  542   V(IfULe,                         A_D, reg, reg, ___) \ |  582   V(IfULe,                         A_D, reg, reg, ___) \ | 
|  543   V(IfULt,                         A_D, reg, reg, ___) \ |  583   V(IfULt,                         A_D, reg, reg, ___) \ | 
|  544   V(IfUGe,                         A_D, reg, reg, ___) \ |  584   V(IfUGe,                         A_D, reg, reg, ___) \ | 
|  545   V(IfUGt,                         A_D, reg, reg, ___) \ |  585   V(IfUGt,                         A_D, reg, reg, ___) \ | 
 |  586   V(IfDNe,                         A_D, reg, reg, ___) \ | 
 |  587   V(IfDEq,                         A_D, reg, reg, ___) \ | 
 |  588   V(IfDLe,                         A_D, reg, reg, ___) \ | 
 |  589   V(IfDLt,                         A_D, reg, reg, ___) \ | 
 |  590   V(IfDGe,                         A_D, reg, reg, ___) \ | 
 |  591   V(IfDGt,                         A_D, reg, reg, ___) \ | 
|  546   V(IfNeStrictNum,                 A_D, reg, reg, ___) \ |  592   V(IfNeStrictNum,                 A_D, reg, reg, ___) \ | 
|  547   V(IfEqStrictNum,                 A_D, reg, reg, ___) \ |  593   V(IfEqStrictNum,                 A_D, reg, reg, ___) \ | 
|  548   V(IfEqNull,                        A, reg, ___, ___) \ |  594   V(IfEqNull,                        A, reg, ___, ___) \ | 
|  549   V(IfNeNull,                        A, reg, ___, ___) \ |  595   V(IfNeNull,                        A, reg, ___, ___) \ | 
|  550   V(CreateArrayTOS,                  0, ___, ___, ___) \ |  596   V(CreateArrayTOS,                  0, ___, ___, ___) \ | 
|  551   V(Allocate,                        D, lit, ___, ___) \ |  597   V(Allocate,                        D, lit, ___, ___) \ | 
|  552   V(AllocateT,                       0, ___, ___, ___) \ |  598   V(AllocateT,                       0, ___, ___, ___) \ | 
|  553   V(StoreIndexedTOS,                 0, ___, ___, ___) \ |  599   V(StoreIndexedTOS,                 0, ___, ___, ___) \ | 
|  554   V(StoreIndexed,                A_B_C, reg, reg, reg) \ |  600   V(StoreIndexed,                A_B_C, reg, reg, reg) \ | 
|  555   V(LoadIndexed,                 A_B_C, reg, reg, reg) \ |  601   V(LoadIndexed,                 A_B_C, reg, reg, reg) \ | 
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|  569   V(CloneContext,                    0, ___, ___, ___) \ |  615   V(CloneContext,                    0, ___, ___, ___) \ | 
|  570   V(MoveSpecial,                   A_D, reg, num, ___) \ |  616   V(MoveSpecial,                   A_D, reg, num, ___) \ | 
|  571   V(InstantiateType,                 D, lit, ___, ___) \ |  617   V(InstantiateType,                 D, lit, ___, ___) \ | 
|  572   V(InstantiateTypeArgumentsTOS,   A_D, num, lit, ___) \ |  618   V(InstantiateTypeArgumentsTOS,   A_D, num, lit, ___) \ | 
|  573   V(InstanceOf,                      A, num, ___, ___) \ |  619   V(InstanceOf,                      A, num, ___, ___) \ | 
|  574   V(AssertAssignable,                D, num, lit, ___) \ |  620   V(AssertAssignable,                D, num, lit, ___) \ | 
|  575   V(AssertBoolean,                   A, num, ___, ___) \ |  621   V(AssertBoolean,                   A, num, ___, ___) \ | 
|  576   V(TestSmi,                       A_D, reg, reg, ___) \ |  622   V(TestSmi,                       A_D, reg, reg, ___) \ | 
|  577   V(TestCids,                      A_D, reg, num, ___) \ |  623   V(TestCids,                      A_D, reg, num, ___) \ | 
|  578   V(CheckSmi,                        A, reg, ___, ___) \ |  624   V(CheckSmi,                        A, reg, ___, ___) \ | 
 |  625   V(CheckEitherNonSmi,             A_D, reg, reg, ___) \ | 
|  579   V(CheckClassId,                  A_D, reg, num, ___) \ |  626   V(CheckClassId,                  A_D, reg, num, ___) \ | 
|  580   V(CheckDenseSwitch,              A_D, reg, num, ___) \ |  627   V(CheckDenseSwitch,              A_D, reg, num, ___) \ | 
|  581   V(CheckCids,                   A_B_C, reg, num, ___) \ |  628   V(CheckCids,                   A_B_C, reg, num, ___) \ | 
|  582   V(CheckStack,                      0, ___, ___, ___) \ |  629   V(CheckStack,                      0, ___, ___, ___) \ | 
|  583   V(DebugStep,                       0, ___, ___, ___) \ |  630   V(DebugStep,                       0, ___, ___, ___) \ | 
|  584   V(DebugBreak,                      A, num, ___, ___) \ |  631   V(DebugBreak,                      A, num, ___, ___) \ | 
|  585   V(Deopt,                         A_D, num, num, ___) \ |  632   V(Deopt,                         A_D, num, num, ___) \ | 
|  586  |  633  | 
|  587 typedef uint32_t Instr; |  634 typedef uint32_t Instr; | 
|  588  |  635  | 
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|  698  |  745  | 
|  699 // After a comparison, the condition NEXT_IS_TRUE means the following |  746 // After a comparison, the condition NEXT_IS_TRUE means the following | 
|  700 // instruction is executed if the comparision is true and skipped over overwise. |  747 // instruction is executed if the comparision is true and skipped over overwise. | 
|  701 // Conidition NEXT_IS_FALSE means the following instruction is executed if the |  748 // Conidition NEXT_IS_FALSE means the following instruction is executed if the | 
|  702 // comparison is false and skipped over otherwise. |  749 // comparison is false and skipped over otherwise. | 
|  703 enum Condition { NEXT_IS_TRUE, NEXT_IS_FALSE }; |  750 enum Condition { NEXT_IS_TRUE, NEXT_IS_FALSE }; | 
|  704  |  751  | 
|  705 }  // namespace dart |  752 }  // namespace dart | 
|  706  |  753  | 
|  707 #endif  // VM_CONSTANTS_DBC_H_ |  754 #endif  // VM_CONSTANTS_DBC_H_ | 
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