X87: [turbofan]: Support using push instructions for setting up tail call parameters.

X87: [turbofan]: Support using push instructions for setting up tail call parameters.

  port bd0d9e7d87d418b0c6a84f298e27058645083dad (r37477)

  original commit message:
  This optimizes the passing of stack parameters in function calls.

  For some architectures (ia32/x64), using pushes when possible instead
  of bumping the stack and then storing parameters generates much
  smaller code, and in some cases is faster (e.g. when a push of a memory
  location can implement a memory-to-memory copy and thus elide an
  intermediate load. On others (e.g. ARM), the benefit is smaller, where
  it's only possible to elide direct stack pointer adjustment in certain cases
  or combine multiple register stores into a single instruction in other limited
  situations. On yet other platforms (ARM64, MIPS), there are no push instructions,
  and this optimization isn't used at all.

  Ideally, this mechanism would be used for both tail calls and normal calls,
  but "normal" calls are currently pretty efficient, and tail calls are very
  inefficient, so this CL sets the bar low for building a new mechanism to
  handle parameter pushing that only needs to raise the bar on tail calls for now.

  The key aspect of this change is that adjustment to the stack pointer
  for tail calls (and perhaps later real calls) is an explicit step separate from
  instruction selection and gap resolution, but aware of both, making it possible
  to safely recognize gap moves that are actually pushes.

BUG=

Committed: https://crrev.com/c140a90c57c66190a85d436d669e903efa700e9d
Cr-Commit-Position: refs/heads/master@{#37508}

[zhengxing.li, 2016-07-05 01:58:32]

zhengxing.li@intel.com changed reviewers:
+ chunyang.dai@intel.com, danno@chromium.org, weiliang.lin@intel.com

[zhengxing.li, 2016-07-05 01:58:32]

PTAL, thanks!

[Weiliang, 2016-07-05 02:06:58]

lgtm

[zhengxing.li, 2016-07-05 02:08:03]

The CQ bit was checked by zhengxing.li@intel.com

[commit-bot: I haz the power, 2016-07-05 02:08:08]

CQ is trying da patch. Follow status at
 
https://chromium-cq-status.appspot.com/v2/patch-status/codereview.chromium.or...

[commit-bot: I haz the power, 2016-07-05 02:32:04]

Committed patchset #1 (id:1)

[commit-bot: I haz the power, 2016-07-05 02:33:45]

Description was changed from

==========
X87: [turbofan]: Support using push instructions for setting up tail call
parameters.

  port bd0d9e7d87d418b0c6a84f298e27058645083dad (r37477)

  original commit message:
  This optimizes the passing of stack parameters in function calls.

  For some architectures (ia32/x64), using pushes when possible instead
  of bumping the stack and then storing parameters generates much
  smaller code, and in some cases is faster (e.g. when a push of a memory
  location can implement a memory-to-memory copy and thus elide an
  intermediate load. On others (e.g. ARM), the benefit is smaller, where
  it's only possible to elide direct stack pointer adjustment in certain cases
  or combine multiple register stores into a single instruction in other limited
  situations. On yet other platforms (ARM64, MIPS), there are no push
instructions,
  and this optimization isn't used at all.

  Ideally, this mechanism would be used for both tail calls and normal calls,
  but "normal" calls are currently pretty efficient, and tail calls are very
  inefficient, so this CL sets the bar low for building a new mechanism to
  handle parameter pushing that only needs to raise the bar on tail calls for
now.

  The key aspect of this change is that adjustment to the stack pointer
  for tail calls (and perhaps later real calls) is an explicit step separate
from
  instruction selection and gap resolution, but aware of both, making it
possible
  to safely recognize gap moves that are actually pushes.

BUG=
==========

to

==========
X87: [turbofan]: Support using push instructions for setting up tail call
parameters.

  port bd0d9e7d87d418b0c6a84f298e27058645083dad (r37477)

  original commit message:
  This optimizes the passing of stack parameters in function calls.

  For some architectures (ia32/x64), using pushes when possible instead
  of bumping the stack and then storing parameters generates much
  smaller code, and in some cases is faster (e.g. when a push of a memory
  location can implement a memory-to-memory copy and thus elide an
  intermediate load. On others (e.g. ARM), the benefit is smaller, where
  it's only possible to elide direct stack pointer adjustment in certain cases
  or combine multiple register stores into a single instruction in other limited
  situations. On yet other platforms (ARM64, MIPS), there are no push
instructions,
  and this optimization isn't used at all.

  Ideally, this mechanism would be used for both tail calls and normal calls,
  but "normal" calls are currently pretty efficient, and tail calls are very
  inefficient, so this CL sets the bar low for building a new mechanism to
  handle parameter pushing that only needs to raise the bar on tail calls for
now.

  The key aspect of this change is that adjustment to the stack pointer
  for tail calls (and perhaps later real calls) is an explicit step separate
from
  instruction selection and gap resolution, but aware of both, making it
possible
  to safely recognize gap moves that are actually pushes.

BUG=

Committed: https://crrev.com/c140a90c57c66190a85d436d669e903efa700e9d
Cr-Commit-Position: refs/heads/master@{#37508}
==========

[commit-bot: I haz the power, 2016-07-05 02:33:46]

Patchset 1 (id:??) landed as
https://crrev.com/c140a90c57c66190a85d436d669e903efa700e9d
Cr-Commit-Position: refs/heads/master@{#37508}