Subzero: Allow deeper levels of variable splitting.

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 450 matching lines @@
   // OperandMIPS32Mem, so in that case it wouldn't need another level of
   // transformation.
   if (auto *Mem = llvm::dyn_cast<OperandMIPS32Mem>(Operand)) {
     return Mem;
   }
 
   // If we didn't do address mode optimization, then we only have a base/offset
   // to work with. MIPS always requires a base register, so just use that to
   // hold the operand.
   auto *Base = llvm::cast<Variable>(legalize(Operand, Legal_Reg));
+  const int32_t Offset = Base->hasStackOffset() ? Base->getStackOffset() : 0;
   return OperandMIPS32Mem::create(
-      Func, Ty, Base, llvm::cast<ConstantInteger32>(
-                          Ctx->getConstantInt32(Base->getStackOffset())));
+      Func, Ty, Base,
+      llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(Offset)));
 }
 
 void TargetMIPS32::emitVariable(const Variable *Var) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   const Type FrameSPTy = IceType_i32;
   if (Var->hasReg()) {
     Str << '$' << getRegName(Var->getRegNum(), Var->getType());
   } else {
@@ skipping 1857 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice