[Turbofan] Instruction::Print can handle SIMD 128 bit registers.

src/compiler/instruction.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/common-operator.h"
 #include "src/compiler/graph.h"
 #include "src/compiler/instruction.h"
 #include "src/compiler/schedule.h"
 #include "src/compiler/state-values-utils.h"
 
@@ skipping 128 matching lines @@
       } else if (op.IsFPStackSlot()) {
         os << "[fp_stack:" << allocated.index();
       } else if (op.IsRegister()) {
         os << "["
            << GetRegConfig()->GetGeneralRegisterName(allocated.register_code())
            << "|R";
       } else if (op.IsDoubleRegister()) {
         os << "["
            << GetRegConfig()->GetDoubleRegisterName(allocated.register_code())
            << "|R";
-      } else {
-        DCHECK(op.IsFloatRegister());
+      } else if (op.IsFloatRegister()) {
         os << "["
            << GetRegConfig()->GetFloatRegisterName(allocated.register_code())
            << "|R";
+      } else {
+        DCHECK(op.IsSimd128Register());
+        os << "["
+           << GetRegConfig()->GetSimd128RegisterName(allocated.register_code())
+           << "|R";
       }
       if (allocated.IsExplicit()) {
         os << "|E";
       }
       switch (allocated.representation()) {
         case MachineRepresentation::kNone:
           os << "|-";
           break;
         case MachineRepresentation::kBit:
           os << "|b";
@@ skipping 859 matching lines @@
   }
   for (int i = 0; i < code.InstructionBlockCount(); i++) {
     printable.sequence_->PrintBlock(printable.register_configuration_, i);
   }
   return os;
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8