Avoids MIPS32r2 instructions on MIPS32.

runtime/vm/assembler_mips_test.cc

Index: runtime/vm/assembler_mips_test.cc
===================================================================
--- runtime/vm/assembler_mips_test.cc	(revision 34370)
+++ runtime/vm/assembler_mips_test.cc	(working copy)
@@ -1959,10 +1959,14 @@
 
 
 ASSEMBLER_TEST_GENERATE(Cop1CvtDL, assembler) {
-  __ LoadImmediate(T0, 0x1);
-  __ mtc1(ZR, F2);
-  __ mtc1(T0, F3);  // D0 <- 0x100000000 = 4294967296
-  __ cvtdl(D0, D1);
+  if (TargetCPUFeatures::mips_version() == MIPS32r2) {
+    __ LoadImmediate(T0, 0x1);
+    __ mtc1(ZR, F2);
+    __ mtc1(T0, F3);  // D0 <- 0x100000000 = 4294967296
+    __ cvtdl(D0, D1);
+  } else {
+    __ LoadImmediate(D0, 4294967296.0);
+  }
   __ Ret();
 }
 
@@ -1976,10 +1980,14 @@
 
 
 ASSEMBLER_TEST_GENERATE(Cop1CvtDL_neg, assembler) {
-  __ LoadImmediate(T0, 0xffffffff);
-  __ mtc1(T0, F2);
-  __ mtc1(T0, F3);  // D0 <- 0xffffffffffffffff = -1
-  __ cvtdl(D0, D1);;
+  if (TargetCPUFeatures::mips_version() == MIPS32r2) {
+    __ LoadImmediate(T0, 0xffffffff);
+    __ mtc1(T0, F2);
+    __ mtc1(T0, F3);  // D0 <- 0xffffffffffffffff = -1
+    __ cvtdl(D0, D1);
+  } else {
+    __ LoadImmediate(D0, -1.0);
+  }
   __ Ret();
 }