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| 1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #include <limits.h> // For LONG_MIN, LONG_MAX. | 5 #include <limits.h> // For LONG_MIN, LONG_MAX. |
| 6 | 6 |
| 7 #if V8_TARGET_ARCH_MIPS64 | 7 #if V8_TARGET_ARCH_MIPS64 |
| 8 | 8 |
| 9 #include "src/base/division-by-constant.h" | 9 #include "src/base/division-by-constant.h" |
| 10 #include "src/bootstrapper.h" | 10 #include "src/bootstrapper.h" |
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| 2502 } | 2502 } |
| 2503 | 2503 |
| 2504 | 2504 |
| 2505 void MacroAssembler::Move(FPURegister dst, float imm) { | 2505 void MacroAssembler::Move(FPURegister dst, float imm) { |
| 2506 li(at, Operand(bit_cast<int32_t>(imm))); | 2506 li(at, Operand(bit_cast<int32_t>(imm))); |
| 2507 mtc1(at, dst); | 2507 mtc1(at, dst); |
| 2508 } | 2508 } |
| 2509 | 2509 |
| 2510 | 2510 |
| 2511 void MacroAssembler::Move(FPURegister dst, double imm) { | 2511 void MacroAssembler::Move(FPURegister dst, double imm) { |
| 2512 static const DoubleRepresentation minus_zero(-0.0); | 2512 int64_t imm_bits = bit_cast<int64_t>(imm); |
| 2513 static const DoubleRepresentation zero(0.0); | |
| 2514 DoubleRepresentation value_rep(imm); | |
| 2515 // Handle special values first. | 2513 // Handle special values first. |
| 2516 if (value_rep == zero && has_double_zero_reg_set_) { | 2514 if (imm_bits == bit_cast<int64_t>(0.0) && has_double_zero_reg_set_) { |
| 2517 mov_d(dst, kDoubleRegZero); | 2515 mov_d(dst, kDoubleRegZero); |
| 2518 } else if (value_rep == minus_zero && has_double_zero_reg_set_) { | 2516 } else if (imm_bits == bit_cast<int64_t>(-0.0) && has_double_zero_reg_set_) { |
| 2519 neg_d(dst, kDoubleRegZero); | 2517 neg_d(dst, kDoubleRegZero); |
| 2520 } else { | 2518 } else { |
| 2521 uint32_t lo, hi; | 2519 uint32_t lo, hi; |
| 2522 DoubleAsTwoUInt32(imm, &lo, &hi); | 2520 DoubleAsTwoUInt32(imm, &lo, &hi); |
| 2523 // Move the low part of the double into the lower bits of the corresponding | 2521 // Move the low part of the double into the lower bits of the corresponding |
| 2524 // FPU register. | 2522 // FPU register. |
| 2525 if (lo != 0) { | 2523 if (lo != 0) { |
| 2526 if (!(lo & kImm16Mask)) { | 2524 if (!(lo & kImm16Mask)) { |
| 2527 lui(at, (lo >> kLuiShift) & kImm16Mask); | 2525 lui(at, (lo >> kLuiShift) & kImm16Mask); |
| 2528 mtc1(at, dst); | 2526 mtc1(at, dst); |
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| 7247 if (mag.shift > 0) sra(result, result, mag.shift); | 7245 if (mag.shift > 0) sra(result, result, mag.shift); |
| 7248 srl(at, dividend, 31); | 7246 srl(at, dividend, 31); |
| 7249 Addu(result, result, Operand(at)); | 7247 Addu(result, result, Operand(at)); |
| 7250 } | 7248 } |
| 7251 | 7249 |
| 7252 | 7250 |
| 7253 } // namespace internal | 7251 } // namespace internal |
| 7254 } // namespace v8 | 7252 } // namespace v8 |
| 7255 | 7253 |
| 7256 #endif // V8_TARGET_ARCH_MIPS64 | 7254 #endif // V8_TARGET_ARCH_MIPS64 |
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