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| 1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #include <limits.h> // For LONG_MIN, LONG_MAX. | 5 #include <limits.h> // For LONG_MIN, LONG_MAX. |
| 6 | 6 |
| 7 #if V8_TARGET_ARCH_MIPS | 7 #if V8_TARGET_ARCH_MIPS |
| 8 | 8 |
| 9 #include "src/base/bits.h" | 9 #include "src/base/bits.h" |
| 10 #include "src/base/division-by-constant.h" | 10 #include "src/base/division-by-constant.h" |
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| 2297 } | 2297 } |
| 2298 | 2298 |
| 2299 | 2299 |
| 2300 void MacroAssembler::Move(FPURegister dst, float imm) { | 2300 void MacroAssembler::Move(FPURegister dst, float imm) { |
| 2301 li(at, Operand(bit_cast<int32_t>(imm))); | 2301 li(at, Operand(bit_cast<int32_t>(imm))); |
| 2302 mtc1(at, dst); | 2302 mtc1(at, dst); |
| 2303 } | 2303 } |
| 2304 | 2304 |
| 2305 | 2305 |
| 2306 void MacroAssembler::Move(FPURegister dst, double imm) { | 2306 void MacroAssembler::Move(FPURegister dst, double imm) { |
| 2307 static const DoubleRepresentation minus_zero(-0.0); | 2307 int64_t imm_bits = bit_cast<int64_t>(imm); |
| 2308 static const DoubleRepresentation zero(0.0); | |
| 2309 DoubleRepresentation value_rep(imm); | |
| 2310 // Handle special values first. | 2308 // Handle special values first. |
| 2311 if (value_rep == zero && has_double_zero_reg_set_) { | 2309 if (imm_bits == bit_cast<int64_t>(0.0) && has_double_zero_reg_set_) { |
| 2312 mov_d(dst, kDoubleRegZero); | 2310 mov_d(dst, kDoubleRegZero); |
| 2313 } else if (value_rep == minus_zero && has_double_zero_reg_set_) { | 2311 } else if (imm_bits == bit_cast<int64_t>(-0.0) && has_double_zero_reg_set_) { |
| 2314 neg_d(dst, kDoubleRegZero); | 2312 neg_d(dst, kDoubleRegZero); |
| 2315 } else { | 2313 } else { |
| 2316 uint32_t lo, hi; | 2314 uint32_t lo, hi; |
| 2317 DoubleAsTwoUInt32(imm, &lo, &hi); | 2315 DoubleAsTwoUInt32(imm, &lo, &hi); |
| 2318 // Move the low part of the double into the lower of the corresponding FPU | 2316 // Move the low part of the double into the lower of the corresponding FPU |
| 2319 // register of FPU register pair. | 2317 // register of FPU register pair. |
| 2320 if (lo != 0) { | 2318 if (lo != 0) { |
| 2321 li(at, Operand(lo)); | 2319 li(at, Operand(lo)); |
| 2322 mtc1(at, dst); | 2320 mtc1(at, dst); |
| 2323 } else { | 2321 } else { |
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| 6910 if (mag.shift > 0) sra(result, result, mag.shift); | 6908 if (mag.shift > 0) sra(result, result, mag.shift); |
| 6911 srl(at, dividend, 31); | 6909 srl(at, dividend, 31); |
| 6912 Addu(result, result, Operand(at)); | 6910 Addu(result, result, Operand(at)); |
| 6913 } | 6911 } |
| 6914 | 6912 |
| 6915 | 6913 |
| 6916 } // namespace internal | 6914 } // namespace internal |
| 6917 } // namespace v8 | 6915 } // namespace v8 |
| 6918 | 6916 |
| 6919 #endif // V8_TARGET_ARCH_MIPS | 6917 #endif // V8_TARGET_ARCH_MIPS |
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