Index: src/ia32/disasm-ia32.cc |
diff --git a/src/ia32/disasm-ia32.cc b/src/ia32/disasm-ia32.cc |
index 8e8039ca412c14ab15e1bbfca53af539fc74fee0..be3530cb3d01f9d4a5328ef2a3f13b9534812a13 100644 |
--- a/src/ia32/disasm-ia32.cc |
+++ b/src/ia32/disasm-ia32.cc |
@@ -1622,11 +1622,19 @@ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer, |
while (*data == 0x66) data++; |
if (*data == 0xf && data[1] == 0x1f) { |
AppendToBuffer("nop"); // 0x66 prefix |
- } else if (*data == 0x90) { |
- AppendToBuffer("nop"); // 0x66 prefix |
- } else if (*data == 0x8B) { |
+ } else if (*data == 0x39) { |
data++; |
- data += PrintOperands("mov_w", REG_OPER_OP_ORDER, data); |
+ data += PrintOperands("cmpw", OPER_REG_OP_ORDER, data); |
+ } else if (*data == 0x3B) { |
+ data++; |
+ data += PrintOperands("cmpw", REG_OPER_OP_ORDER, data); |
+ } else if (*data == 0x81) { |
+ data++; |
+ AppendToBuffer("cmpw "); |
+ data += PrintRightOperand(data); |
+ int imm = *reinterpret_cast<int16_t*>(data); |
+ AppendToBuffer(",0x%x", imm); |
+ data += 2; |
} else if (*data == 0x87) { |
data++; |
int mod, regop, rm; |
@@ -1640,6 +1648,11 @@ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer, |
AppendToBuffer("mov_w "); |
data += PrintRightOperand(data); |
AppendToBuffer(",%s", NameOfCPURegister(regop)); |
+ } else if (*data == 0x8B) { |
+ data++; |
+ data += PrintOperands("mov_w", REG_OPER_OP_ORDER, data); |
+ } else if (*data == 0x90) { |
+ AppendToBuffer("nop"); // 0x66 prefix |
} else if (*data == 0xC7) { |
data++; |
AppendToBuffer("%s ", "mov_w"); |