MIPS: [turbofan] Fix addition for deoptimization.

src/mips/macro-assembler-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>  // For LONG_MIN, LONG_MAX.
 
 #if V8_TARGET_ARCH_MIPS
 
 #include "src/base/bits.h"
 #include "src/base/division-by-constant.h"
@@ skipping 5475 matching lines @@
     Register overflow_dst = t9;
     DCHECK(!dst.is(scratch));
     DCHECK(!dst.is(overflow_dst));
     DCHECK(!scratch.is(overflow_dst));
     DCHECK(!left.is(overflow_dst));
     DCHECK(!right.is(overflow_dst));
     DCHECK(!left.is(scratch));
     DCHECK(!right.is(scratch));
 
     if (left.is(right) && dst.is(left)) {
-      mov(overflow_dst, right);
-      right = overflow_dst;
-    }
-
-    if (dst.is(left)) {
+      mov(scratch, left);                // Preserve left and right.
+      addu(dst, left, right);            // Both are overwritten.
+      xor_(overflow_dst, dst, scratch);  // Left and right are equal.
+      Label done;                        // Restore inputs if overflow.
+      Branch(&done, ge, overflow_dst, Operand(zero_reg));
+      mov(left, scratch);  // Original left and right.
+      bind(&done);
+    } else if (dst.is(left)) {
       mov(scratch, left);           // Preserve left.
       addu(dst, left, right);       // Left is overwritten.
       xor_(scratch, dst, scratch);  // Original left.
       xor_(overflow_dst, dst, right);
       and_(overflow_dst, overflow_dst, scratch);
     } else if (dst.is(right)) {
       mov(scratch, right);          // Preserve right.
       addu(dst, left, right);       // Right is overwritten.
       xor_(scratch, dst, scratch);  // Original right.
       xor_(overflow_dst, dst, left);
@@ skipping 1401 matching lines @@
   if (mag.shift > 0) sra(result, result, mag.shift);
   srl(at, dividend, 31);
   Addu(result, result, Operand(at));
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS