| OLD | NEW |
| 1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
| 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
| 7 | 7 |
| 8 namespace v8 { | 8 namespace v8 { |
| 9 namespace internal { | 9 namespace internal { |
| 10 namespace compiler { | 10 namespace compiler { |
| 11 | 11 |
| 12 // MIPS64-specific opcodes that specify which assembly sequence to emit. | 12 // MIPS64-specific opcodes that specify which assembly sequence to emit. |
| 13 // Most opcodes specify a single instruction. | 13 // Most opcodes specify a single instruction. |
| 14 #define TARGET_ARCH_OPCODE_LIST(V) \ | 14 #define TARGET_ARCH_OPCODE_LIST(V) \ |
| 15 V(Mips64Add) \ | 15 V(Mips64Add) \ |
| 16 V(Mips64Dadd) \ | 16 V(Mips64Dadd) \ |
| 17 V(Mips64DaddOvf) \ | 17 V(Mips64DaddOvf) \ |
| 18 V(Mips64Sub) \ | 18 V(Mips64Sub) \ |
| 19 V(Mips64Dsub) \ | 19 V(Mips64Dsub) \ |
| 20 V(Mips64DsubOvf) \ | 20 V(Mips64DsubOvf) \ |
| 21 V(Mips64Mul) \ | 21 V(Mips64Mul) \ |
| 22 V(Mips64MulOvf) \ |
| 22 V(Mips64MulHigh) \ | 23 V(Mips64MulHigh) \ |
| 23 V(Mips64DMulHigh) \ | 24 V(Mips64DMulHigh) \ |
| 24 V(Mips64MulHighU) \ | 25 V(Mips64MulHighU) \ |
| 25 V(Mips64Dmul) \ | 26 V(Mips64Dmul) \ |
| 26 V(Mips64Div) \ | 27 V(Mips64Div) \ |
| 27 V(Mips64Ddiv) \ | 28 V(Mips64Ddiv) \ |
| 28 V(Mips64DivU) \ | 29 V(Mips64DivU) \ |
| 29 V(Mips64DdivU) \ | 30 V(Mips64DdivU) \ |
| 30 V(Mips64Mod) \ | 31 V(Mips64Mod) \ |
| 31 V(Mips64Dmod) \ | 32 V(Mips64Dmod) \ |
| (...skipping 131 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 163 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 164 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
| 164 V(MRI) /* [%r0 + K] */ \ | 165 V(MRI) /* [%r0 + K] */ \ |
| 165 V(MRR) /* [%r0 + %r1] */ | 166 V(MRR) /* [%r0 + %r1] */ |
| 166 | 167 |
| 167 | 168 |
| 168 } // namespace compiler | 169 } // namespace compiler |
| 169 } // namespace internal | 170 } // namespace internal |
| 170 } // namespace v8 | 171 } // namespace v8 |
| 171 | 172 |
| 172 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 173 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
| OLD | NEW |