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Side by Side Diff: src/compiler/mips/instruction-codes-mips.h

Issue 2101123005: [turbofan] Introduce integer multiplication with overflow. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: REBASE. Created 4 years, 5 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
11 11
12 // MIPS-specific opcodes that specify which assembly sequence to emit. 12 // MIPS-specific opcodes that specify which assembly sequence to emit.
13 // Most opcodes specify a single instruction. 13 // Most opcodes specify a single instruction.
14 #define TARGET_ARCH_OPCODE_LIST(V) \ 14 #define TARGET_ARCH_OPCODE_LIST(V) \
15 V(MipsAdd) \ 15 V(MipsAdd) \
16 V(MipsAddOvf) \ 16 V(MipsAddOvf) \
17 V(MipsSub) \ 17 V(MipsSub) \
18 V(MipsSubOvf) \ 18 V(MipsSubOvf) \
19 V(MipsMul) \ 19 V(MipsMul) \
20 V(MipsMulOvf) \
20 V(MipsMulHigh) \ 21 V(MipsMulHigh) \
21 V(MipsMulHighU) \ 22 V(MipsMulHighU) \
22 V(MipsDiv) \ 23 V(MipsDiv) \
23 V(MipsDivU) \ 24 V(MipsDivU) \
24 V(MipsMod) \ 25 V(MipsMod) \
25 V(MipsModU) \ 26 V(MipsModU) \
26 V(MipsAnd) \ 27 V(MipsAnd) \
27 V(MipsOr) \ 28 V(MipsOr) \
28 V(MipsNor) \ 29 V(MipsNor) \
29 V(MipsXor) \ 30 V(MipsXor) \
(...skipping 104 matching lines...) Expand 10 before | Expand all | Expand 10 after
134 #define TARGET_ADDRESSING_MODE_LIST(V) \ 135 #define TARGET_ADDRESSING_MODE_LIST(V) \
135 V(MRI) /* [%r0 + K] */ \ 136 V(MRI) /* [%r0 + K] */ \
136 V(MRR) /* [%r0 + %r1] */ 137 V(MRR) /* [%r0 + %r1] */
137 138
138 139
139 } // namespace compiler 140 } // namespace compiler
140 } // namespace internal 141 } // namespace internal
141 } // namespace v8 142 } // namespace v8
142 143
143 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 144 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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