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Side by Side Diff: src/compiler/mips/code-generator-mips.cc

Issue 2101123005: [turbofan] Introduce integer multiplication with overflow. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: REBASE. Created 4 years, 5 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/ast/scopes.h" 5 #include "src/ast/scopes.h"
6 #include "src/compiler/code-generator.h" 6 #include "src/compiler/code-generator.h"
7 #include "src/compiler/code-generator-impl.h" 7 #include "src/compiler/code-generator-impl.h"
8 #include "src/compiler/gap-resolver.h" 8 #include "src/compiler/gap-resolver.h"
9 #include "src/compiler/node-matchers.h" 9 #include "src/compiler/node-matchers.h"
10 #include "src/compiler/osr.h" 10 #include "src/compiler/osr.h"
(...skipping 818 matching lines...) Expand 10 before | Expand all | Expand 10 after
829 break; 829 break;
830 case kMipsSub: 830 case kMipsSub:
831 __ Subu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 831 __ Subu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
832 break; 832 break;
833 case kMipsSubOvf: 833 case kMipsSubOvf:
834 // Pseudo-instruction used for overflow/branch. No opcode emitted here. 834 // Pseudo-instruction used for overflow/branch. No opcode emitted here.
835 break; 835 break;
836 case kMipsMul: 836 case kMipsMul:
837 __ Mul(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 837 __ Mul(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
838 break; 838 break;
839 case kMipsMulOvf:
840 // Pseudo-instruction used for overflow/branch. No opcode emitted here.
841 break;
839 case kMipsMulHigh: 842 case kMipsMulHigh:
840 __ Mulh(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 843 __ Mulh(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
841 break; 844 break;
842 case kMipsMulHighU: 845 case kMipsMulHighU:
843 __ Mulhu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 846 __ Mulhu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
844 break; 847 break;
845 case kMipsDiv: 848 case kMipsDiv:
846 __ Div(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); 849 __ Div(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
847 if (IsMipsArchVariant(kMips32r6)) { 850 if (IsMipsArchVariant(kMips32r6)) {
848 __ selnez(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); 851 __ selnez(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
(...skipping 738 matching lines...) Expand 10 before | Expand all | Expand 10 after
1587 i.InputOperand(1), tlabel, flabel); 1590 i.InputOperand(1), tlabel, flabel);
1588 break; 1591 break;
1589 case kNotOverflow: 1592 case kNotOverflow:
1590 __ SubBranchOvf(i.OutputRegister(), i.InputRegister(0), 1593 __ SubBranchOvf(i.OutputRegister(), i.InputRegister(0),
1591 i.InputOperand(1), flabel, tlabel); 1594 i.InputOperand(1), flabel, tlabel);
1592 break; 1595 break;
1593 default: 1596 default:
1594 UNSUPPORTED_COND(kMipsAddOvf, branch->condition); 1597 UNSUPPORTED_COND(kMipsAddOvf, branch->condition);
1595 break; 1598 break;
1596 } 1599 }
1600 } else if (instr->arch_opcode() == kMipsMulOvf) {
1601 switch (branch->condition) {
1602 case kOverflow:
1603 __ MulBranchOvf(i.OutputRegister(), i.InputRegister(0),
1604 i.InputOperand(1), tlabel, flabel);
1605 break;
1606 case kNotOverflow:
1607 __ MulBranchOvf(i.OutputRegister(), i.InputRegister(0),
1608 i.InputOperand(1), flabel, tlabel);
1609 break;
1610 default:
1611 UNSUPPORTED_COND(kMipsMulOvf, branch->condition);
1612 break;
1613 }
1597 } else if (instr->arch_opcode() == kMipsCmp) { 1614 } else if (instr->arch_opcode() == kMipsCmp) {
1598 cc = FlagsConditionToConditionCmp(branch->condition); 1615 cc = FlagsConditionToConditionCmp(branch->condition);
1599 __ Branch(tlabel, cc, i.InputRegister(0), i.InputOperand(1)); 1616 __ Branch(tlabel, cc, i.InputRegister(0), i.InputOperand(1));
1600 } else if (instr->arch_opcode() == kMipsCmpS) { 1617 } else if (instr->arch_opcode() == kMipsCmpS) {
1601 if (!convertCondition(branch->condition, cc)) { 1618 if (!convertCondition(branch->condition, cc)) {
1602 UNSUPPORTED_COND(kMips64CmpS, branch->condition); 1619 UNSUPPORTED_COND(kMips64CmpS, branch->condition);
1603 } 1620 }
1604 FPURegister left = i.InputOrZeroSingleRegister(0); 1621 FPURegister left = i.InputOrZeroSingleRegister(0);
1605 FPURegister right = i.InputOrZeroSingleRegister(1); 1622 FPURegister right = i.InputOrZeroSingleRegister(1);
1606 if ((left.is(kDoubleRegZero) || right.is(kDoubleRegZero)) && 1623 if ((left.is(kDoubleRegZero) || right.is(kDoubleRegZero)) &&
(...skipping 45 matching lines...) Expand 10 before | Expand all | Expand 10 after
1652 if (instr->arch_opcode() == kMipsTst) { 1669 if (instr->arch_opcode() == kMipsTst) {
1653 cc = FlagsConditionToConditionTst(condition); 1670 cc = FlagsConditionToConditionTst(condition);
1654 __ And(kScratchReg, i.InputRegister(0), i.InputOperand(1)); 1671 __ And(kScratchReg, i.InputRegister(0), i.InputOperand(1));
1655 __ Sltu(result, zero_reg, kScratchReg); 1672 __ Sltu(result, zero_reg, kScratchReg);
1656 if (cc == eq) { 1673 if (cc == eq) {
1657 // Sltu produces 0 for equality, invert the result. 1674 // Sltu produces 0 for equality, invert the result.
1658 __ xori(result, result, 1); 1675 __ xori(result, result, 1);
1659 } 1676 }
1660 return; 1677 return;
1661 } else if (instr->arch_opcode() == kMipsAddOvf || 1678 } else if (instr->arch_opcode() == kMipsAddOvf ||
1662 instr->arch_opcode() == kMipsSubOvf) { 1679 instr->arch_opcode() == kMipsSubOvf ||
1680 instr->arch_opcode() == kMipsMulOvf) {
1663 Label flabel, tlabel; 1681 Label flabel, tlabel;
1664 switch (instr->arch_opcode()) { 1682 switch (instr->arch_opcode()) {
1665 case kMipsAddOvf: 1683 case kMipsAddOvf:
1666 __ AddBranchNoOvf(i.OutputRegister(), i.InputRegister(0), 1684 __ AddBranchNoOvf(i.OutputRegister(), i.InputRegister(0),
1667 i.InputOperand(1), &flabel); 1685 i.InputOperand(1), &flabel);
1668 1686
1669 break; 1687 break;
1670 case kMipsSubOvf: 1688 case kMipsSubOvf:
1671 __ SubBranchNoOvf(i.OutputRegister(), i.InputRegister(0), 1689 __ SubBranchNoOvf(i.OutputRegister(), i.InputRegister(0),
1672 i.InputOperand(1), &flabel); 1690 i.InputOperand(1), &flabel);
1673 break; 1691 break;
1692 case kMipsMulOvf:
1693 __ MulBranchNoOvf(i.OutputRegister(), i.InputRegister(0),
1694 i.InputOperand(1), &flabel);
1695 break;
1674 default: 1696 default:
1675 UNREACHABLE(); 1697 UNREACHABLE();
1676 break; 1698 break;
1677 } 1699 }
1678 __ li(result, 1); 1700 __ li(result, 1);
1679 __ Branch(&tlabel); 1701 __ Branch(&tlabel);
1680 __ bind(&flabel); 1702 __ bind(&flabel);
1681 __ li(result, 0); 1703 __ li(result, 0);
1682 __ bind(&tlabel); 1704 __ bind(&tlabel);
1683 } else if (instr->arch_opcode() == kMipsCmp) { 1705 } else if (instr->arch_opcode() == kMipsCmp) {
(...skipping 450 matching lines...) Expand 10 before | Expand all | Expand 10 after
2134 padding_size -= v8::internal::Assembler::kInstrSize; 2156 padding_size -= v8::internal::Assembler::kInstrSize;
2135 } 2157 }
2136 } 2158 }
2137 } 2159 }
2138 2160
2139 #undef __ 2161 #undef __
2140 2162
2141 } // namespace compiler 2163 } // namespace compiler
2142 } // namespace internal 2164 } // namespace internal
2143 } // namespace v8 2165 } // namespace v8
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