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Side by Side Diff: src/compiler/arm64/code-generator-arm64.cc

Issue 2101123005: [turbofan] Introduce integer multiplication with overflow. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: REBASE. Created 4 years, 5 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/compiler/code-generator.h" 5 #include "src/compiler/code-generator.h"
6 6
7 #include "src/arm64/frames-arm64.h" 7 #include "src/arm64/frames-arm64.h"
8 #include "src/arm64/macro-assembler-arm64.h" 8 #include "src/arm64/macro-assembler-arm64.h"
9 #include "src/ast/scopes.h" 9 #include "src/ast/scopes.h"
10 #include "src/compiler/code-generator-impl.h" 10 #include "src/compiler/code-generator-impl.h"
(...skipping 101 matching lines...) Expand 10 before | Expand all | Expand 10 after
112 case kMode_Operand2_R_ROR_I: 112 case kMode_Operand2_R_ROR_I:
113 return Operand(InputRegister32(index), ROR, InputInt5(index + 1)); 113 return Operand(InputRegister32(index), ROR, InputInt5(index + 1));
114 case kMode_Operand2_R_UXTB: 114 case kMode_Operand2_R_UXTB:
115 return Operand(InputRegister32(index), UXTB); 115 return Operand(InputRegister32(index), UXTB);
116 case kMode_Operand2_R_UXTH: 116 case kMode_Operand2_R_UXTH:
117 return Operand(InputRegister32(index), UXTH); 117 return Operand(InputRegister32(index), UXTH);
118 case kMode_Operand2_R_SXTB: 118 case kMode_Operand2_R_SXTB:
119 return Operand(InputRegister32(index), SXTB); 119 return Operand(InputRegister32(index), SXTB);
120 case kMode_Operand2_R_SXTH: 120 case kMode_Operand2_R_SXTH:
121 return Operand(InputRegister32(index), SXTH); 121 return Operand(InputRegister32(index), SXTH);
122 case kMode_Operand2_R_SXTW:
123 return Operand(InputRegister32(index), SXTW);
122 case kMode_MRI: 124 case kMode_MRI:
123 case kMode_MRR: 125 case kMode_MRR:
124 break; 126 break;
125 } 127 }
126 UNREACHABLE(); 128 UNREACHABLE();
127 return Operand(-1); 129 return Operand(-1);
128 } 130 }
129 131
130 Operand InputOperand2_64(size_t index) { 132 Operand InputOperand2_64(size_t index) {
131 switch (AddressingModeField::decode(instr_->opcode())) { 133 switch (AddressingModeField::decode(instr_->opcode())) {
132 case kMode_None: 134 case kMode_None:
133 return InputOperand64(index); 135 return InputOperand64(index);
134 case kMode_Operand2_R_LSL_I: 136 case kMode_Operand2_R_LSL_I:
135 return Operand(InputRegister64(index), LSL, InputInt6(index + 1)); 137 return Operand(InputRegister64(index), LSL, InputInt6(index + 1));
136 case kMode_Operand2_R_LSR_I: 138 case kMode_Operand2_R_LSR_I:
137 return Operand(InputRegister64(index), LSR, InputInt6(index + 1)); 139 return Operand(InputRegister64(index), LSR, InputInt6(index + 1));
138 case kMode_Operand2_R_ASR_I: 140 case kMode_Operand2_R_ASR_I:
139 return Operand(InputRegister64(index), ASR, InputInt6(index + 1)); 141 return Operand(InputRegister64(index), ASR, InputInt6(index + 1));
140 case kMode_Operand2_R_ROR_I: 142 case kMode_Operand2_R_ROR_I:
141 return Operand(InputRegister64(index), ROR, InputInt6(index + 1)); 143 return Operand(InputRegister64(index), ROR, InputInt6(index + 1));
142 case kMode_Operand2_R_UXTB: 144 case kMode_Operand2_R_UXTB:
143 return Operand(InputRegister64(index), UXTB); 145 return Operand(InputRegister64(index), UXTB);
144 case kMode_Operand2_R_UXTH: 146 case kMode_Operand2_R_UXTH:
145 return Operand(InputRegister64(index), UXTH); 147 return Operand(InputRegister64(index), UXTH);
146 case kMode_Operand2_R_SXTB: 148 case kMode_Operand2_R_SXTB:
147 return Operand(InputRegister64(index), SXTB); 149 return Operand(InputRegister64(index), SXTB);
148 case kMode_Operand2_R_SXTH: 150 case kMode_Operand2_R_SXTH:
149 return Operand(InputRegister64(index), SXTH); 151 return Operand(InputRegister64(index), SXTH);
152 case kMode_Operand2_R_SXTW:
153 return Operand(InputRegister32(index), SXTW);
150 case kMode_MRI: 154 case kMode_MRI:
151 case kMode_MRR: 155 case kMode_MRR:
152 break; 156 break;
153 } 157 }
154 UNREACHABLE(); 158 UNREACHABLE();
155 return Operand(-1); 159 return Operand(-1);
156 } 160 }
157 161
158 MemOperand MemoryOperand(size_t* first_index) { 162 MemOperand MemoryOperand(size_t* first_index) {
159 const size_t index = *first_index; 163 const size_t index = *first_index;
160 switch (AddressingModeField::decode(instr_->opcode())) { 164 switch (AddressingModeField::decode(instr_->opcode())) {
161 case kMode_None: 165 case kMode_None:
162 case kMode_Operand2_R_LSR_I: 166 case kMode_Operand2_R_LSR_I:
163 case kMode_Operand2_R_ASR_I: 167 case kMode_Operand2_R_ASR_I:
164 case kMode_Operand2_R_ROR_I: 168 case kMode_Operand2_R_ROR_I:
165 case kMode_Operand2_R_UXTB: 169 case kMode_Operand2_R_UXTB:
166 case kMode_Operand2_R_UXTH: 170 case kMode_Operand2_R_UXTH:
167 case kMode_Operand2_R_SXTB: 171 case kMode_Operand2_R_SXTB:
168 case kMode_Operand2_R_SXTH: 172 case kMode_Operand2_R_SXTH:
173 case kMode_Operand2_R_SXTW:
169 break; 174 break;
170 case kMode_Operand2_R_LSL_I: 175 case kMode_Operand2_R_LSL_I:
171 *first_index += 3; 176 *first_index += 3;
172 return MemOperand(InputRegister(index + 0), InputRegister(index + 1), 177 return MemOperand(InputRegister(index + 0), InputRegister(index + 1),
173 LSL, InputInt32(index + 2)); 178 LSL, InputInt32(index + 2));
174 case kMode_MRI: 179 case kMode_MRI:
175 *first_index += 2; 180 *first_index += 2;
176 return MemOperand(InputRegister(index + 0), InputInt32(index + 1)); 181 return MemOperand(InputRegister(index + 0), InputInt32(index + 1));
177 case kMode_MRR: 182 case kMode_MRR:
178 *first_index += 2; 183 *first_index += 2;
(...skipping 1069 matching lines...) Expand 10 before | Expand all | Expand 10 after
1248 case kArm64Clz32: 1253 case kArm64Clz32:
1249 __ Clz(i.OutputRegister32(), i.InputRegister32(0)); 1254 __ Clz(i.OutputRegister32(), i.InputRegister32(0));
1250 break; 1255 break;
1251 case kArm64Rbit: 1256 case kArm64Rbit:
1252 __ Rbit(i.OutputRegister64(), i.InputRegister64(0)); 1257 __ Rbit(i.OutputRegister64(), i.InputRegister64(0));
1253 break; 1258 break;
1254 case kArm64Rbit32: 1259 case kArm64Rbit32:
1255 __ Rbit(i.OutputRegister32(), i.InputRegister32(0)); 1260 __ Rbit(i.OutputRegister32(), i.InputRegister32(0));
1256 break; 1261 break;
1257 case kArm64Cmp: 1262 case kArm64Cmp:
1258 __ Cmp(i.InputOrZeroRegister64(0), i.InputOperand(1)); 1263 if (AddressingModeField::decode(opcode) == kMode_Operand2_R_SXTW) {
1264 __ Cmp(i.InputOrZeroRegister64(0), i.InputOperand2_32(1));
1265 } else {
1266 __ Cmp(i.InputOrZeroRegister64(0), i.InputOperand(1));
1267 }
1259 break; 1268 break;
1260 case kArm64Cmp32: 1269 case kArm64Cmp32:
1261 __ Cmp(i.InputOrZeroRegister32(0), i.InputOperand2_32(1)); 1270 __ Cmp(i.InputOrZeroRegister32(0), i.InputOperand2_32(1));
1262 break; 1271 break;
1263 case kArm64Cmn: 1272 case kArm64Cmn:
1264 __ Cmn(i.InputOrZeroRegister64(0), i.InputOperand(1)); 1273 __ Cmn(i.InputOrZeroRegister64(0), i.InputOperand(1));
1265 break; 1274 break;
1266 case kArm64Cmn32: 1275 case kArm64Cmn32:
1267 __ Cmn(i.InputOrZeroRegister32(0), i.InputOperand2_32(1)); 1276 __ Cmn(i.InputOrZeroRegister32(0), i.InputOperand2_32(1));
1268 break; 1277 break;
(...skipping 789 matching lines...) Expand 10 before | Expand all | Expand 10 after
2058 padding_size -= kInstructionSize; 2067 padding_size -= kInstructionSize;
2059 } 2068 }
2060 } 2069 }
2061 } 2070 }
2062 2071
2063 #undef __ 2072 #undef __
2064 2073
2065 } // namespace compiler 2074 } // namespace compiler
2066 } // namespace internal 2075 } // namespace internal
2067 } // namespace v8 2076 } // namespace v8
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