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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ | 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ | 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
11 | 11 |
12 // ARM-specific opcodes that specify which assembly sequence to emit. | 12 // ARM-specific opcodes that specify which assembly sequence to emit. |
13 // Most opcodes specify a single instruction. | 13 // Most opcodes specify a single instruction. |
14 #define TARGET_ARCH_OPCODE_LIST(V) \ | 14 #define TARGET_ARCH_OPCODE_LIST(V) \ |
15 V(ArmAdd) \ | 15 V(ArmAdd) \ |
16 V(ArmAnd) \ | 16 V(ArmAnd) \ |
17 V(ArmBic) \ | 17 V(ArmBic) \ |
18 V(ArmClz) \ | 18 V(ArmClz) \ |
19 V(ArmCmp) \ | 19 V(ArmCmp) \ |
20 V(ArmCmn) \ | 20 V(ArmCmn) \ |
21 V(ArmTst) \ | 21 V(ArmTst) \ |
22 V(ArmTeq) \ | 22 V(ArmTeq) \ |
23 V(ArmOrr) \ | 23 V(ArmOrr) \ |
24 V(ArmEor) \ | 24 V(ArmEor) \ |
25 V(ArmSub) \ | 25 V(ArmSub) \ |
26 V(ArmRsb) \ | 26 V(ArmRsb) \ |
27 V(ArmMul) \ | 27 V(ArmMul) \ |
28 V(ArmMla) \ | 28 V(ArmMla) \ |
29 V(ArmMls) \ | 29 V(ArmMls) \ |
| 30 V(ArmSmull) \ |
30 V(ArmSmmul) \ | 31 V(ArmSmmul) \ |
31 V(ArmSmmla) \ | 32 V(ArmSmmla) \ |
32 V(ArmUmull) \ | 33 V(ArmUmull) \ |
33 V(ArmSdiv) \ | 34 V(ArmSdiv) \ |
34 V(ArmUdiv) \ | 35 V(ArmUdiv) \ |
35 V(ArmMov) \ | 36 V(ArmMov) \ |
36 V(ArmMvn) \ | 37 V(ArmMvn) \ |
37 V(ArmBfc) \ | 38 V(ArmBfc) \ |
38 V(ArmUbfx) \ | 39 V(ArmUbfx) \ |
39 V(ArmSbfx) \ | 40 V(ArmSbfx) \ |
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135 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ | 136 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ |
136 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ | 137 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ |
137 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ | 138 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ |
138 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ | 139 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ |
139 | 140 |
140 } // namespace compiler | 141 } // namespace compiler |
141 } // namespace internal | 142 } // namespace internal |
142 } // namespace v8 | 143 } // namespace v8 |
143 | 144 |
144 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ | 145 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ |
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