Subzero: Fix Calling Convention for MIPS O32 abi

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 541 matching lines @@
   GPRegsUsed |= RegisterAliases[*Reg];
   return true;
 }
 
 inline void TargetMIPS32::CallingConv::discardNextGPRAndItsAliases(
     CfgVector<RegNumT> *Regs) {
   GPRegsUsed |= RegisterAliases[Regs->back()];
   Regs->pop_back();
 }
 
+inline void TargetMIPS32::CallingConv::alignGPR(CfgVector<RegNumT> *Regs) {
+  if (Regs->back() == RegMIPS32::Reg_A1 || Regs->back() == RegMIPS32::Reg_A3)
+    discardNextGPRAndItsAliases(Regs);
+}
+
 // GPR are not packed when passing parameters. Thus, a function foo(i32, i64,
 // i32) will have the first argument in a0, the second in a2-a3, and the third
 // on the stack. To model this behavior, whenever we pop a register from Regs,
 // we remove all of its aliases from the pool of available GPRs. This has the
 // effect of computing the "closure" on the GPR registers.
 void TargetMIPS32::CallingConv::discardUnavailableGPRsAndTheirAliases(
     CfgVector<RegNumT> *Regs) {
   while (!Regs->empty() && GPRegsUsed[Regs->back()]) {
     discardNextGPRAndItsAliases(Regs);
   }
@@ skipping 24 matching lines @@
 
   *Reg = Source->back();
   VFPRegsUsed |= RegisterAliases[*Reg];
 
   // In MIPS O32 abi if fun arguments are (f32, i32) then one can not use reg_a0
   // for second argument even though it's free. f32 arg goes in reg_f12, i32 arg
   // goes in reg_a1. Similarly if arguments are (f64, i32) second argument goes
   // in reg_a3 and a0, a1 are not used.
   Source = &GPRArgs;
   // Discard one GPR reg for f32(4 bytes), two for f64(4 + 4 bytes)
+  if (Ty == IceType_f64) {
+    // In MIPS o32 abi, when we use GPR argument pairs to store F64 values, pair
+    // must be aligned at even register. Similarly when we discard GPR registers
+    // when some arguments from starting 16 bytes goes in FPR, we must take care
+    // of alignment. For example if fun args are (f32, f64, f32), for first f32
+    // we discard a0, now for f64 argument, which will go in F14F15, we must
+    // first align GPR vector to even register by discarding a1, then discard
+    // two GPRs a2 and a3. Now last f32 argument will go on stack.
+    alignGPR(Source);
+    discardNextGPRAndItsAliases(Source);
+  }
   discardNextGPRAndItsAliases(Source);
-  if (Ty == IceType_f64)
-    discardNextGPRAndItsAliases(Source);
-
   return true;
 }
 
 void TargetMIPS32::CallingConv::discardUnavailableVFPRegsAndTheirAliases(
     CfgVector<RegNumT> *Regs) {
   while (!Regs->empty() && VFPRegsUsed[Regs->back()]) {
     Regs->pop_back();
   }
 }
 
@@ skipping 1708 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice