OLD | NEW |
1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
(...skipping 478 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
489 bool argInReg(Type Ty, uint32_t ArgNo, RegNumT *Reg); | 489 bool argInReg(Type Ty, uint32_t ArgNo, RegNumT *Reg); |
490 | 490 |
491 private: | 491 private: |
492 // argInGPR is used to find if any GPR register is available for argument of | 492 // argInGPR is used to find if any GPR register is available for argument of |
493 // type Ty | 493 // type Ty |
494 bool argInGPR(Type Ty, RegNumT *Reg); | 494 bool argInGPR(Type Ty, RegNumT *Reg); |
495 /// argInVFP is to floating-point/vector types what argInGPR is for integer | 495 /// argInVFP is to floating-point/vector types what argInGPR is for integer |
496 /// types. | 496 /// types. |
497 bool argInVFP(Type Ty, RegNumT *Reg); | 497 bool argInVFP(Type Ty, RegNumT *Reg); |
498 inline void discardNextGPRAndItsAliases(CfgVector<RegNumT> *Regs); | 498 inline void discardNextGPRAndItsAliases(CfgVector<RegNumT> *Regs); |
| 499 inline void alignGPR(CfgVector<RegNumT> *Regs); |
499 void discardUnavailableGPRsAndTheirAliases(CfgVector<RegNumT> *Regs); | 500 void discardUnavailableGPRsAndTheirAliases(CfgVector<RegNumT> *Regs); |
500 SmallBitVector GPRegsUsed; | 501 SmallBitVector GPRegsUsed; |
501 CfgVector<RegNumT> GPRArgs; | 502 CfgVector<RegNumT> GPRArgs; |
502 CfgVector<RegNumT> I64Args; | 503 CfgVector<RegNumT> I64Args; |
503 | 504 |
504 void discardUnavailableVFPRegsAndTheirAliases(CfgVector<RegNumT> *Regs); | 505 void discardUnavailableVFPRegsAndTheirAliases(CfgVector<RegNumT> *Regs); |
505 SmallBitVector VFPRegsUsed; | 506 SmallBitVector VFPRegsUsed; |
506 CfgVector<RegNumT> FP32Args; | 507 CfgVector<RegNumT> FP32Args; |
507 CfgVector<RegNumT> FP64Args; | 508 CfgVector<RegNumT> FP64Args; |
508 // UseFPRegs is a flag indicating if FP registers can be used | 509 // UseFPRegs is a flag indicating if FP registers can be used |
(...skipping 167 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
676 explicit TargetHeaderMIPS32(GlobalContext *Ctx); | 677 explicit TargetHeaderMIPS32(GlobalContext *Ctx); |
677 | 678 |
678 private: | 679 private: |
679 ~TargetHeaderMIPS32() = default; | 680 ~TargetHeaderMIPS32() = default; |
680 }; | 681 }; |
681 | 682 |
682 } // end of namespace MIPS32 | 683 } // end of namespace MIPS32 |
683 } // end of namespace Ice | 684 } // end of namespace Ice |
684 | 685 |
685 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H | 686 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H |
OLD | NEW |