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Unified Diff: src/IceInstX8664.def

Issue 2100333002: Reorder X8664 Register Defs so that scratch registers are allocated first (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 6 months ago
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Index: src/IceInstX8664.def
diff --git a/src/IceInstX8664.def b/src/IceInstX8664.def
index ad686c7cb59ef597a58361cdf79c3d3c6d479524..0a46c0879284bbcb0fe7f7d9d74fe6e0a0abf7ec 100644
--- a/src/IceInstX8664.def
+++ b/src/IceInstX8664.def
@@ -54,12 +54,6 @@
REGLIST3(RegX8664, rcx, ecx, cx)) \
X(Reg_dl, 2, "dl", Reg_rdx, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
REGLIST3(RegX8664, rdx, edx, dx)) \
- X(Reg_bl, 3, "bl", Reg_rbx, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
- REGLIST3(RegX8664, rbx, ebx, bx)) \
- X(Reg_spl, 4, "spl", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
- REGLIST3(RegX8664, rsp, esp, sp)) \
- X(Reg_bpl, 5, "bpl", Reg_rbp, 0,1,0,1,1, 1,0,0,0,1, 0, 0,0,0,1,0, \
- REGLIST3(RegX8664, rbp, ebp, bp)) \
X(Reg_sil, 6, "sil", Reg_rsi, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
REGLIST3(RegX8664, rsi, esi, si)) \
X(Reg_dil, 7, "dil", Reg_rdi, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
@@ -72,6 +66,12 @@
REGLIST3(RegX8664, r10, r10d, r10w)) \
X(Reg_r11l, 11, "r11b", Reg_r11, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
REGLIST3(RegX8664, r11, r11d, r11w)) \
+ X(Reg_spl, 4, "spl", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
Jim Stichnoth 2016/06/27 22:06:55 Can you arrange the encoding order to be 3/4/5 ins
manasijm 2016/06/27 22:37:09 Done.
+ REGLIST3(RegX8664, rsp, esp, sp)) \
+ X(Reg_bl, 3, "bl", Reg_rbx, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
+ REGLIST3(RegX8664, rbx, ebx, bx)) \
+ X(Reg_bpl, 5, "bpl", Reg_rbp, 0,1,0,1,1, 1,0,0,0,1, 0, 0,0,0,1,0, \
+ REGLIST3(RegX8664, rbp, ebp, bp)) \
X(Reg_r12l, 12, "r12b", Reg_r12, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
REGLIST3(RegX8664, r12, r12d, r12w)) \
X(Reg_r13l, 13, "r13b", Reg_r13, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
@@ -105,12 +105,6 @@
REGLIST4(RegX8664, ecx, cx, cl, ch)) \
X(Reg_rdx, 2, "rdx", Reg_rdx, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
REGLIST4(RegX8664, edx, dx, dl, dh)) \
- X(Reg_rbx, 3, "rbx", Reg_rbx, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
- REGLIST4(RegX8664, ebx, bx, bl, bh)) \
- X(Reg_rsp, 4, "rsp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 1,0,0,0,0, \
- REGLIST3(RegX8664, esp, sp, spl)) \
- X(Reg_rbp, 5, "rbp", Reg_rbp, 0,1,0,1,1, 1,1,0,0,0, 0, 1,0,0,0,0, \
- REGLIST3(RegX8664, ebp, bp, bpl)) \
X(Reg_rsi, 6, "rsi", Reg_rsi, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
REGLIST3(RegX8664, esi, si, sil)) \
X(Reg_rdi, 7, "rdi", Reg_rdi, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
@@ -123,6 +117,12 @@
REGLIST3(RegX8664, r10d, r10w, r10l)) \
X(Reg_r11, 11, "r11", Reg_r11, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
REGLIST3(RegX8664, r11d, r11w, r11l)) \
+ X(Reg_rsp, 4, "rsp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 1,0,0,0,0, \
+ REGLIST3(RegX8664, esp, sp, spl)) \
+ X(Reg_rbx, 3, "rbx", Reg_rbx, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
+ REGLIST4(RegX8664, ebx, bx, bl, bh)) \
+ X(Reg_rbp, 5, "rbp", Reg_rbp, 0,1,0,1,1, 1,1,0,0,0, 0, 1,0,0,0,0, \
+ REGLIST3(RegX8664, ebp, bp, bpl)) \
X(Reg_r12, 12, "r12", Reg_r12, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
REGLIST3(RegX8664, r12d, r12w, r12l)) \
X(Reg_r13, 13, "r13", Reg_r13, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
@@ -138,12 +138,6 @@
REGLIST4(RegX8664, rcx, cx, cl, ch)) \
X(Reg_edx, 2, "edx", Reg_rdx, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
REGLIST4(RegX8664, rdx, dx, dl, dh)) \
- X(Reg_ebx, 3, "ebx", Reg_rbx, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
- REGLIST4(RegX8664, rbx, bx, bl, bh)) \
- X(Reg_esp, 4, "esp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
- REGLIST3(RegX8664, rsp, sp, spl)) \
- X(Reg_ebp, 5, "ebp", Reg_rbp, 0,1,0,1,1, 1,0,1,0,0, 0, 0,1,0,0,0, \
- REGLIST3(RegX8664, rbp, bp, bpl)) \
X(Reg_esi, 6, "esi", Reg_rsi, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
REGLIST3(RegX8664, rsi, si, sil)) \
X(Reg_edi, 7, "edi", Reg_rdi, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
@@ -156,6 +150,12 @@
REGLIST3(RegX8664, r10, r10w, r10l)) \
X(Reg_r11d, 11, "r11d", Reg_r11, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
REGLIST3(RegX8664, r11, r11w, r11l)) \
+ X(Reg_esp, 4, "esp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, rsp, sp, spl)) \
+ X(Reg_ebx, 3, "ebx", Reg_rbx, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST4(RegX8664, rbx, bx, bl, bh)) \
+ X(Reg_ebp, 5, "ebp", Reg_rbp, 0,1,0,1,1, 1,0,1,0,0, 0, 0,1,0,0,0, \
+ REGLIST3(RegX8664, rbp, bp, bpl)) \
X(Reg_r12d, 12, "r12d", Reg_r12, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
REGLIST3(RegX8664, r12, r12w, r12l)) \
X(Reg_r13d, 13, "r13d", Reg_r13, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
@@ -171,12 +171,6 @@
REGLIST4(RegX8664, rcx, ecx, cl, ch)) \
X(Reg_dx, 2, "dx", Reg_rdx, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
REGLIST4(RegX8664, rdx, edx, dl, dh)) \
- X(Reg_bx, 3, "bx", Reg_rbx, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
- REGLIST4(RegX8664, rbx, ebx, bl, bh)) \
- X(Reg_sp, 4, "sp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
- REGLIST3(RegX8664, rsp, esp, spl)) \
- X(Reg_bp, 5, "bp", Reg_rbp, 0,1,0,1,1, 1,0,0,1,0, 0, 0,0,1,0,0, \
- REGLIST3(RegX8664, rbp, ebp, bpl)) \
X(Reg_si, 6, "si", Reg_rsi, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
REGLIST3(RegX8664, rsi, esi, sil)) \
X(Reg_di, 7, "di", Reg_rdi, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
@@ -189,6 +183,12 @@
REGLIST3(RegX8664, r10, r10d, r10l)) \
X(Reg_r11w, 11, "r11w", Reg_r11, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
REGLIST3(RegX8664, r11, r11d, r11l)) \
+ X(Reg_sp, 4, "sp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
+ REGLIST3(RegX8664, rsp, esp, spl)) \
+ X(Reg_bx, 3, "bx", Reg_rbx, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST4(RegX8664, rbx, ebx, bl, bh)) \
+ X(Reg_bp, 5, "bp", Reg_rbp, 0,1,0,1,1, 1,0,0,1,0, 0, 0,0,1,0,0, \
+ REGLIST3(RegX8664, rbp, ebp, bpl)) \
X(Reg_r12w, 12, "r12w", Reg_r12, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
REGLIST3(RegX8664, r12, r12d, r12l)) \
X(Reg_r13w, 13, "r13w", Reg_r13, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
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