Reorder X8664 Register Defs so that scratch registers are allocated first

src/IceInstX8664.cpp

 //===- subzero/src/IceInstX8664.cpp - X86-64 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 143 matching lines @@
   }
 
   Str << "(";
   if (Base != nullptr) {
     const Variable *B = Base;
     if (!NeedSandboxing) {
       // TODO(jpp): stop abusing the operand's type to identify LEAs.
       const Type MemType = getType();
       if (Base->getType() != IceType_i32 && MemType != IceType_void) {
         // X86-64 is ILP32, but %rsp and %rbp are accessed as 64-bit registers.
-        // For filetype=asm, they need to be emitted as their 32-bit sibilings.
+        // For filetype=asm, they need to be emitted as their 32-bit siblings.
         assert(Base->getType() == IceType_i64);
-        assert(Base->getRegNum() == RegX8664::Encoded_Reg_rsp ||
-               Base->getRegNum() == RegX8664::Encoded_Reg_rbp ||
+        assert(getEncodedGPR(Base->getRegNum()) == RegX8664::Encoded_Reg_rsp ||
+               getEncodedGPR(Base->getRegNum()) == RegX8664::Encoded_Reg_rbp ||
                getType() == IceType_void);
         B = B->asType(Func, IceType_i32, X8664::Traits::getGprForType(
                                              IceType_i32, Base->getRegNum()));
       }
     }
 
     B->emit(Func);
   }
 
   if (Index != nullptr) {
@@ skipping 175 matching lines @@
     Var->dump(Func);
   else
     Var->dump(Str);
   Str << ")";
 }
 
 } // namespace X8664
 } // end of namespace Ice
 
 X86INSTS_DEFINE_STATIC_DATA(X8664, X8664::Traits)