src/IceInstX8664.def - Issue 2100333002: Reorder X8664 Register Defs so that scratch registers are allocated first

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Issue 2100333002: Reorder X8664 Register Defs so that scratch registers are allocated first (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master

Patch Set: Created 4 years, 5 months ago

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1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -- C++ --===//	1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -- C++ --===//

2 //	2 //

3 // The Subzero Code Generator	3 // The Subzero Code Generator

4 //	4 //

5 // This file is distributed under the University of Illinois Open Source	5 // This file is distributed under the University of Illinois Open Source

6 // License. See LICENSE.TXT for details.	6 // License. See LICENSE.TXT for details.

7 //	7 //

8 //===----------------------------------------------------------------------===//	8 //===----------------------------------------------------------------------===//

9 //	9 //

10 // This file defines properties of lowered x86-64 instructions in the	10 // This file defines properties of lowered x86-64 instructions in the

11 // form of x-macros.	11 // form of x-macros.

12 //	12 //

13 //===----------------------------------------------------------------------===//	13 //===----------------------------------------------------------------------===//

14	14

15 #ifndef SUBZERO_SRC_ICEINSTX8664_DEF	15 #ifndef SUBZERO_SRC_ICEINSTX8664_DEF

16 #define SUBZERO_SRC_ICEINSTX8664_DEF	16 #define SUBZERO_SRC_ICEINSTX8664_DEF

17	17

18 #include "IceRegList.h"	18 #include "IceRegList.h"

19	19

20 // x86-64 ABI:	20 // x86-64 ABI:

21 // Scratch GPRs: rax, rcx, rdx, rsi, rdi, r8, r9, r10, r11	21 // Scratch GPRs: rax, rcx, rdx, rsi, rdi, r8, r9, r10, r11

22 // Callee-save GPRs: rbx, rbp, r12, r13, r14, r15	22 // Callee-save GPRs: rbx, rbp, r12, r13, r14, r15

23 // Scratch XMMs: xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,	23 // Scratch XMMs: xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,

24 // xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15	24 // xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15
	Jim Stichnoth 2016/06/27 22:06:55 Here it would be good to add a comment that the sc Here it would be good to add a comment that the scratch registers are listed first, followed by preserved registers, so that the register allocator will favor scratch registers.
25 // Key to table columns:	25 // Key to table columns:

26 // val: Enum value, when a specific register is needed during lowering.	26 // val: Enum value, when a specific register is needed during lowering.

27 // encode: Encoding in the integrated assembler.	27 // encode: Encoding in the integrated assembler.

28 // name: Name used for the external assembler.	28 // name: Name used for the external assembler.

29 // scratch: Scratch (caller-save) register.	29 // scratch: Scratch (caller-save) register.

30 // preserved: Preserved (callee-save) register.	30 // preserved: Preserved (callee-save) register.

31 // stackptr: This register is used as the stack pointer.	31 // stackptr: This register is used as the stack pointer.

32 // frameptr: This register is used as the frame pointer if needed.	32 // frameptr: This register is used as the frame pointer if needed.

33 // sboxres: This register is reserved in sandboxing.	33 // sboxres: This register is reserved in sandboxing.

34 // isGPR: This is a GPR (integer-type).	34 // isGPR: This is a GPR (integer-type).

(...skipping 12 matching lines...) Expand all Loading...
47 /* val, encode, name, base, scratch,preserved,stackptr,frameptr,sboxres, \	47 /* val, encode, name, base, scratch,preserved,stackptr,frameptr,sboxres, \

48 isGPR,is64,is32,is16,is8, isXmm, \	48 isGPR,is64,is32,is16,is8, isXmm, \

49 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \	49 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \

50 /* 8-bit registers */ \	50 /* 8-bit registers */ \

51 X(Reg_al, 0, "al", Reg_rax, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \	51 X(Reg_al, 0, "al", Reg_rax, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \

52 REGLIST3(RegX8664, rax, eax, ax)) \	52 REGLIST3(RegX8664, rax, eax, ax)) \

53 X(Reg_cl, 1, "cl", Reg_rcx, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \	53 X(Reg_cl, 1, "cl", Reg_rcx, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \

54 REGLIST3(RegX8664, rcx, ecx, cx)) \	54 REGLIST3(RegX8664, rcx, ecx, cx)) \

55 X(Reg_dl, 2, "dl", Reg_rdx, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \	55 X(Reg_dl, 2, "dl", Reg_rdx, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \

56 REGLIST3(RegX8664, rdx, edx, dx)) \	56 REGLIST3(RegX8664, rdx, edx, dx)) \

57 X(Reg_bl, 3, "bl", Reg_rbx, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \

58 REGLIST3(RegX8664, rbx, ebx, bx)) \

59 X(Reg_spl, 4, "spl", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \

60 REGLIST3(RegX8664, rsp, esp, sp)) \

61 X(Reg_bpl, 5, "bpl", Reg_rbp, 0,1,0,1,1, 1,0,0,0,1, 0, 0,0,0,1,0, \

62 REGLIST3(RegX8664, rbp, ebp, bp)) \

63 X(Reg_sil, 6, "sil", Reg_rsi, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \	57 X(Reg_sil, 6, "sil", Reg_rsi, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \

64 REGLIST3(RegX8664, rsi, esi, si)) \	58 REGLIST3(RegX8664, rsi, esi, si)) \

65 X(Reg_dil, 7, "dil", Reg_rdi, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \	59 X(Reg_dil, 7, "dil", Reg_rdi, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \

66 REGLIST3(RegX8664, rdi, edi, di)) \	60 REGLIST3(RegX8664, rdi, edi, di)) \

67 X(Reg_r8l, 8, "r8b", Reg_r8, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \	61 X(Reg_r8l, 8, "r8b", Reg_r8, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \

68 REGLIST3(RegX8664, r8, r8d, r8w)) \	62 REGLIST3(RegX8664, r8, r8d, r8w)) \

69 X(Reg_r9l, 9, "r9b", Reg_r9, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \	63 X(Reg_r9l, 9, "r9b", Reg_r9, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \

70 REGLIST3(RegX8664, r9, r9d, r9w)) \	64 REGLIST3(RegX8664, r9, r9d, r9w)) \

71 X(Reg_r10l, 10, "r10b", Reg_r10, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \	65 X(Reg_r10l, 10, "r10b", Reg_r10, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \

72 REGLIST3(RegX8664, r10, r10d, r10w)) \	66 REGLIST3(RegX8664, r10, r10d, r10w)) \

73 X(Reg_r11l, 11, "r11b", Reg_r11, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \	67 X(Reg_r11l, 11, "r11b", Reg_r11, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \

74 REGLIST3(RegX8664, r11, r11d, r11w)) \	68 REGLIST3(RegX8664, r11, r11d, r11w)) \

	69 X(Reg_spl, 4, "spl", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
	Jim Stichnoth 2016/06/27 22:06:55 Can you arrange the encoding order to be 3/4/5 ins Can you arrange the encoding order to be 3/4/5 instead of 4/3/5? manasijm 2016/06/27 22:37:09 Done. Show quoted text On 2016/06/27 22:06:55, stichnot wrote: > Can you arrange the encoding order to be 3/4/5 instead of 4/3/5? Done.
	70 REGLIST3(RegX8664, rsp, esp, sp)) \

	71 X(Reg_bl, 3, "bl", Reg_rbx, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \

	72 REGLIST3(RegX8664, rbx, ebx, bx)) \

	73 X(Reg_bpl, 5, "bpl", Reg_rbp, 0,1,0,1,1, 1,0,0,0,1, 0, 0,0,0,1,0, \

	74 REGLIST3(RegX8664, rbp, ebp, bp)) \

75 X(Reg_r12l, 12, "r12b", Reg_r12, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \	75 X(Reg_r12l, 12, "r12b", Reg_r12, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \

76 REGLIST3(RegX8664, r12, r12d, r12w)) \	76 REGLIST3(RegX8664, r12, r12d, r12w)) \

77 X(Reg_r13l, 13, "r13b", Reg_r13, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \	77 X(Reg_r13l, 13, "r13b", Reg_r13, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \

78 REGLIST3(RegX8664, r13, r13d, r13w)) \	78 REGLIST3(RegX8664, r13, r13d, r13w)) \

79 X(Reg_r14l, 14, "r14b", Reg_r14, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \	79 X(Reg_r14l, 14, "r14b", Reg_r14, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \

80 REGLIST3(RegX8664, r14, r14d, r14w)) \	80 REGLIST3(RegX8664, r14, r14d, r14w)) \

81 X(Reg_r15l, 15, "r15b", Reg_r15, 0,1,0,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \	81 X(Reg_r15l, 15, "r15b", Reg_r15, 0,1,0,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \

82 REGLIST3(RegX8664, r15, r15d, r15w)) \	82 REGLIST3(RegX8664, r15, r15d, r15w)) \

83 /* High 8-bit registers. None are allowed for register allocation. */ \	83 /* High 8-bit registers. None are allowed for register allocation. */ \

84 X(Reg_ah, 4, "ah", Reg_rax, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \	84 X(Reg_ah, 4, "ah", Reg_rax, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \

(...skipping 13 matching lines...) Expand all Loading...
98 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \	98 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \

99 isGPR,is64,is32,is16,is8, isXmm, \	99 isGPR,is64,is32,is16,is8, isXmm, \

100 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \	100 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \

101 /* 64-bit registers */ \	101 /* 64-bit registers */ \

102 X(Reg_rax, 0, "rax", Reg_rax, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \	102 X(Reg_rax, 0, "rax", Reg_rax, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \

103 REGLIST4(RegX8664, eax, ax, al, ah)) \	103 REGLIST4(RegX8664, eax, ax, al, ah)) \

104 X(Reg_rcx, 1, "rcx", Reg_rcx, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \	104 X(Reg_rcx, 1, "rcx", Reg_rcx, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \

105 REGLIST4(RegX8664, ecx, cx, cl, ch)) \	105 REGLIST4(RegX8664, ecx, cx, cl, ch)) \

106 X(Reg_rdx, 2, "rdx", Reg_rdx, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \	106 X(Reg_rdx, 2, "rdx", Reg_rdx, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \

107 REGLIST4(RegX8664, edx, dx, dl, dh)) \	107 REGLIST4(RegX8664, edx, dx, dl, dh)) \

108 X(Reg_rbx, 3, "rbx", Reg_rbx, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \

109 REGLIST4(RegX8664, ebx, bx, bl, bh)) \

110 X(Reg_rsp, 4, "rsp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 1,0,0,0,0, \

111 REGLIST3(RegX8664, esp, sp, spl)) \

112 X(Reg_rbp, 5, "rbp", Reg_rbp, 0,1,0,1,1, 1,1,0,0,0, 0, 1,0,0,0,0, \

113 REGLIST3(RegX8664, ebp, bp, bpl)) \

114 X(Reg_rsi, 6, "rsi", Reg_rsi, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \	108 X(Reg_rsi, 6, "rsi", Reg_rsi, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \

115 REGLIST3(RegX8664, esi, si, sil)) \	109 REGLIST3(RegX8664, esi, si, sil)) \

116 X(Reg_rdi, 7, "rdi", Reg_rdi, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \	110 X(Reg_rdi, 7, "rdi", Reg_rdi, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \

117 REGLIST3(RegX8664, edi, di, dil)) \	111 REGLIST3(RegX8664, edi, di, dil)) \

118 X(Reg_r8, 8, "r8", Reg_r8, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \	112 X(Reg_r8, 8, "r8", Reg_r8, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \

119 REGLIST3(RegX8664, r8d, r8w, r8l)) \	113 REGLIST3(RegX8664, r8d, r8w, r8l)) \

120 X(Reg_r9, 9, "r9", Reg_r9, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \	114 X(Reg_r9, 9, "r9", Reg_r9, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \

121 REGLIST3(RegX8664, r9d, r9w, r9l)) \	115 REGLIST3(RegX8664, r9d, r9w, r9l)) \

122 X(Reg_r10, 10, "r10", Reg_r10, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \	116 X(Reg_r10, 10, "r10", Reg_r10, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \

123 REGLIST3(RegX8664, r10d, r10w, r10l)) \	117 REGLIST3(RegX8664, r10d, r10w, r10l)) \

124 X(Reg_r11, 11, "r11", Reg_r11, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \	118 X(Reg_r11, 11, "r11", Reg_r11, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \

125 REGLIST3(RegX8664, r11d, r11w, r11l)) \	119 REGLIST3(RegX8664, r11d, r11w, r11l)) \

	120 X(Reg_rsp, 4, "rsp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 1,0,0,0,0, \

	121 REGLIST3(RegX8664, esp, sp, spl)) \

	122 X(Reg_rbx, 3, "rbx", Reg_rbx, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \

	123 REGLIST4(RegX8664, ebx, bx, bl, bh)) \

	124 X(Reg_rbp, 5, "rbp", Reg_rbp, 0,1,0,1,1, 1,1,0,0,0, 0, 1,0,0,0,0, \

	125 REGLIST3(RegX8664, ebp, bp, bpl)) \

126 X(Reg_r12, 12, "r12", Reg_r12, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \	126 X(Reg_r12, 12, "r12", Reg_r12, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \

127 REGLIST3(RegX8664, r12d, r12w, r12l)) \	127 REGLIST3(RegX8664, r12d, r12w, r12l)) \

128 X(Reg_r13, 13, "r13", Reg_r13, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \	128 X(Reg_r13, 13, "r13", Reg_r13, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \

129 REGLIST3(RegX8664, r13d, r13w, r13l)) \	129 REGLIST3(RegX8664, r13d, r13w, r13l)) \

130 X(Reg_r14, 14, "r14", Reg_r14, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \	130 X(Reg_r14, 14, "r14", Reg_r14, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \

131 REGLIST3(RegX8664, r14d, r14w, r14l)) \	131 REGLIST3(RegX8664, r14d, r14w, r14l)) \

132 X(Reg_r15, 15, "r15", Reg_r15, 0,1,0,0,1, 1,1,0,0,0, 0, 1,0,0,0,0, \	132 X(Reg_r15, 15, "r15", Reg_r15, 0,1,0,0,1, 1,1,0,0,0, 0, 1,0,0,0,0, \

133 REGLIST3(RegX8664, r15d, r15w, r15l)) \	133 REGLIST3(RegX8664, r15d, r15w, r15l)) \

134 /* 32-bit registers */ \	134 /* 32-bit registers */ \

135 X(Reg_eax, 0, "eax", Reg_rax, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \	135 X(Reg_eax, 0, "eax", Reg_rax, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \

136 REGLIST4(RegX8664, rax, ax, al, ah)) \	136 REGLIST4(RegX8664, rax, ax, al, ah)) \

137 X(Reg_ecx, 1, "ecx", Reg_rcx, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \	137 X(Reg_ecx, 1, "ecx", Reg_rcx, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \

138 REGLIST4(RegX8664, rcx, cx, cl, ch)) \	138 REGLIST4(RegX8664, rcx, cx, cl, ch)) \

139 X(Reg_edx, 2, "edx", Reg_rdx, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \	139 X(Reg_edx, 2, "edx", Reg_rdx, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \

140 REGLIST4(RegX8664, rdx, dx, dl, dh)) \	140 REGLIST4(RegX8664, rdx, dx, dl, dh)) \

141 X(Reg_ebx, 3, "ebx", Reg_rbx, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \

142 REGLIST4(RegX8664, rbx, bx, bl, bh)) \

143 X(Reg_esp, 4, "esp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \

144 REGLIST3(RegX8664, rsp, sp, spl)) \

145 X(Reg_ebp, 5, "ebp", Reg_rbp, 0,1,0,1,1, 1,0,1,0,0, 0, 0,1,0,0,0, \

146 REGLIST3(RegX8664, rbp, bp, bpl)) \

147 X(Reg_esi, 6, "esi", Reg_rsi, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \	141 X(Reg_esi, 6, "esi", Reg_rsi, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \

148 REGLIST3(RegX8664, rsi, si, sil)) \	142 REGLIST3(RegX8664, rsi, si, sil)) \

149 X(Reg_edi, 7, "edi", Reg_rdi, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \	143 X(Reg_edi, 7, "edi", Reg_rdi, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \

150 REGLIST3(RegX8664, rdi, di, dil)) \	144 REGLIST3(RegX8664, rdi, di, dil)) \

151 X(Reg_r8d, 8, "r8d", Reg_r8, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \	145 X(Reg_r8d, 8, "r8d", Reg_r8, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \

152 REGLIST3(RegX8664, r8, r8w, r8l)) \	146 REGLIST3(RegX8664, r8, r8w, r8l)) \

153 X(Reg_r9d, 9, "r9d", Reg_r9, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \	147 X(Reg_r9d, 9, "r9d", Reg_r9, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \

154 REGLIST3(RegX8664, r9, r9w, r9l)) \	148 REGLIST3(RegX8664, r9, r9w, r9l)) \

155 X(Reg_r10d, 10, "r10d", Reg_r10, 1,0,0,1,0, 1,0,1,0,0, 0, 0,1,0,0,0, \	149 X(Reg_r10d, 10, "r10d", Reg_r10, 1,0,0,1,0, 1,0,1,0,0, 0, 0,1,0,0,0, \

156 REGLIST3(RegX8664, r10, r10w, r10l)) \	150 REGLIST3(RegX8664, r10, r10w, r10l)) \

157 X(Reg_r11d, 11, "r11d", Reg_r11, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \	151 X(Reg_r11d, 11, "r11d", Reg_r11, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \

158 REGLIST3(RegX8664, r11, r11w, r11l)) \	152 REGLIST3(RegX8664, r11, r11w, r11l)) \

	153 X(Reg_esp, 4, "esp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \

	154 REGLIST3(RegX8664, rsp, sp, spl)) \

	155 X(Reg_ebx, 3, "ebx", Reg_rbx, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \

	156 REGLIST4(RegX8664, rbx, bx, bl, bh)) \

	157 X(Reg_ebp, 5, "ebp", Reg_rbp, 0,1,0,1,1, 1,0,1,0,0, 0, 0,1,0,0,0, \

	158 REGLIST3(RegX8664, rbp, bp, bpl)) \

159 X(Reg_r12d, 12, "r12d", Reg_r12, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \	159 X(Reg_r12d, 12, "r12d", Reg_r12, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \

160 REGLIST3(RegX8664, r12, r12w, r12l)) \	160 REGLIST3(RegX8664, r12, r12w, r12l)) \

161 X(Reg_r13d, 13, "r13d", Reg_r13, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \	161 X(Reg_r13d, 13, "r13d", Reg_r13, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \

162 REGLIST3(RegX8664, r13, r13w, r13l)) \	162 REGLIST3(RegX8664, r13, r13w, r13l)) \

163 X(Reg_r14d, 14, "r14d", Reg_r14, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \	163 X(Reg_r14d, 14, "r14d", Reg_r14, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \

164 REGLIST3(RegX8664, r14, r14w, r14l)) \	164 REGLIST3(RegX8664, r14, r14w, r14l)) \

165 X(Reg_r15d, 15, "r15d", Reg_r15, 0,1,0,0,1, 1,0,1,0,0, 0, 0,1,0,0,0, \	165 X(Reg_r15d, 15, "r15d", Reg_r15, 0,1,0,0,1, 1,0,1,0,0, 0, 0,1,0,0,0, \

166 REGLIST3(RegX8664, r15, r15w, r15l)) \	166 REGLIST3(RegX8664, r15, r15w, r15l)) \

167 /* 16-bit registers */ \	167 /* 16-bit registers */ \

168 X(Reg_ax, 0, "ax", Reg_rax, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \	168 X(Reg_ax, 0, "ax", Reg_rax, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \

169 REGLIST4(RegX8664, rax, eax, al, ah)) \	169 REGLIST4(RegX8664, rax, eax, al, ah)) \

170 X(Reg_cx, 1, "cx", Reg_rcx, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \	170 X(Reg_cx, 1, "cx", Reg_rcx, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \

171 REGLIST4(RegX8664, rcx, ecx, cl, ch)) \	171 REGLIST4(RegX8664, rcx, ecx, cl, ch)) \

172 X(Reg_dx, 2, "dx", Reg_rdx, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \	172 X(Reg_dx, 2, "dx", Reg_rdx, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \

173 REGLIST4(RegX8664, rdx, edx, dl, dh)) \	173 REGLIST4(RegX8664, rdx, edx, dl, dh)) \

174 X(Reg_bx, 3, "bx", Reg_rbx, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \

175 REGLIST4(RegX8664, rbx, ebx, bl, bh)) \

176 X(Reg_sp, 4, "sp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \

177 REGLIST3(RegX8664, rsp, esp, spl)) \

178 X(Reg_bp, 5, "bp", Reg_rbp, 0,1,0,1,1, 1,0,0,1,0, 0, 0,0,1,0,0, \

179 REGLIST3(RegX8664, rbp, ebp, bpl)) \

180 X(Reg_si, 6, "si", Reg_rsi, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \	174 X(Reg_si, 6, "si", Reg_rsi, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \

181 REGLIST3(RegX8664, rsi, esi, sil)) \	175 REGLIST3(RegX8664, rsi, esi, sil)) \

182 X(Reg_di, 7, "di", Reg_rdi, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \	176 X(Reg_di, 7, "di", Reg_rdi, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \

183 REGLIST3(RegX8664, rdi, edi, dil)) \	177 REGLIST3(RegX8664, rdi, edi, dil)) \

184 X(Reg_r8w, 8, "r8w", Reg_r8, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \	178 X(Reg_r8w, 8, "r8w", Reg_r8, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \

185 REGLIST3(RegX8664, r8, r8d, r8l)) \	179 REGLIST3(RegX8664, r8, r8d, r8l)) \

186 X(Reg_r9w, 9, "r9w", Reg_r9, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \	180 X(Reg_r9w, 9, "r9w", Reg_r9, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \

187 REGLIST3(RegX8664, r9, r9d, r9l)) \	181 REGLIST3(RegX8664, r9, r9d, r9l)) \

188 X(Reg_r10w, 10, "r10w", Reg_r10, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \	182 X(Reg_r10w, 10, "r10w", Reg_r10, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \

189 REGLIST3(RegX8664, r10, r10d, r10l)) \	183 REGLIST3(RegX8664, r10, r10d, r10l)) \

190 X(Reg_r11w, 11, "r11w", Reg_r11, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \	184 X(Reg_r11w, 11, "r11w", Reg_r11, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \

191 REGLIST3(RegX8664, r11, r11d, r11l)) \	185 REGLIST3(RegX8664, r11, r11d, r11l)) \

	186 X(Reg_sp, 4, "sp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \

	187 REGLIST3(RegX8664, rsp, esp, spl)) \

	188 X(Reg_bx, 3, "bx", Reg_rbx, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \

	189 REGLIST4(RegX8664, rbx, ebx, bl, bh)) \

	190 X(Reg_bp, 5, "bp", Reg_rbp, 0,1,0,1,1, 1,0,0,1,0, 0, 0,0,1,0,0, \

	191 REGLIST3(RegX8664, rbp, ebp, bpl)) \

192 X(Reg_r12w, 12, "r12w", Reg_r12, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \	192 X(Reg_r12w, 12, "r12w", Reg_r12, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \

193 REGLIST3(RegX8664, r12, r12d, r12l)) \	193 REGLIST3(RegX8664, r12, r12d, r12l)) \

194 X(Reg_r13w, 13, "r13w", Reg_r13, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \	194 X(Reg_r13w, 13, "r13w", Reg_r13, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \

195 REGLIST3(RegX8664, r13, r13d, r13l)) \	195 REGLIST3(RegX8664, r13, r13d, r13l)) \

196 X(Reg_r14w, 14, "r14w", Reg_r14, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \	196 X(Reg_r14w, 14, "r14w", Reg_r14, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \

197 REGLIST3(RegX8664, r14, r14d, r14l)) \	197 REGLIST3(RegX8664, r14, r14d, r14l)) \

198 X(Reg_r15w, 15, "r15w", Reg_r15, 0,1,0,0,1, 1,0,0,1,0, 0, 0,0,1,0,0, \	198 X(Reg_r15w, 15, "r15w", Reg_r15, 0,1,0,0,1, 1,0,0,1,0, 0, 0,0,1,0,0, \

199 REGLIST3(RegX8664, r15, r15d, r15l)) \	199 REGLIST3(RegX8664, r15, r15d, r15l)) \

200 /* 8-bit registers */ \	200 /* 8-bit registers */ \

201 REGX8664_BYTEREG_TABLE \	201 REGX8664_BYTEREG_TABLE \

(...skipping 103 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
305 X(v4i1, i32, "?", "", "", "", "d", "dq", "", "") \	305 X(v4i1, i32, "?", "", "", "", "d", "dq", "", "") \

306 X(v8i1, i16, "?", "", "", "", "w", "wd", "", "") \	306 X(v8i1, i16, "?", "", "", "", "w", "wd", "", "") \

307 X(v16i1, i8, "?", "", "", "", "b", "bw", "", "") \	307 X(v16i1, i8, "?", "", "", "", "b", "bw", "", "") \

308 X(v16i8, i8, "?", "", "", "", "b", "bw", "", "") \	308 X(v16i8, i8, "?", "", "", "", "b", "bw", "", "") \

309 X(v8i16, i16, "?", "", "", "", "w", "wd", "", "") \	309 X(v8i16, i16, "?", "", "", "", "w", "wd", "", "") \

310 X(v4i32, i32, "dq", "", "", "", "d", "dq", "", "") \	310 X(v4i32, i32, "dq", "", "", "", "d", "dq", "", "") \

311 X(v4f32, f32, "ps", "", "ps", "ps", "d", "dq", "", "")	311 X(v4f32, f32, "ps", "", "ps", "ps", "d", "dq", "", "")

312 //#define X(tag, elementty, cvt, sdss, pdps, pack, unpack, width, fld)	312 //#define X(tag, elementty, cvt, sdss, pdps, pack, unpack, width, fld)

313	313

314 #endif // SUBZERO_SRC_ICEINSTX8664_DEF	314 #endif // SUBZERO_SRC_ICEINSTX8664_DEF

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