ARM64: optimize call immediate

src/arm64/macro-assembler-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 2006 matching lines @@
   // address is loaded.
   positions_recorder()->WriteRecordedPositions();
 
   // Addresses always have 64 bits, so we shouldn't encounter NONE32.
   ASSERT(rmode != RelocInfo::NONE32);
 
   UseScratchRegisterScope temps(this);
   Register temp = temps.AcquireX();
 
   if (rmode == RelocInfo::NONE64) {
+    // Addresses are 48 bits so we never need to load the upper 16 bits.

[ulan, 2014/03/24 12:45:54]

ASSERT_EQ(0, ((imm >> 48) & 0xffff));

     uint64_t imm = reinterpret_cast<uint64_t>(target);
     movz(temp, (imm >> 0) & 0xffff, 0);
-    movk(temp, (imm >> 16) & 0xffff, 16);
-    movk(temp, (imm >> 32) & 0xffff, 32);
-    movk(temp, (imm >> 48) & 0xffff, 48);
+    if (predictable_code_size()) {
+      movk(temp, (imm >> 16) & 0xffff, 16);
+      movk(temp, (imm >> 32) & 0xffff, 32);
+    } else {
+      if (((imm >> 16) & 0xffff) != 0) movk(temp, (imm >> 16) & 0xffff, 16);
+      if (((imm >> 32) & 0xffff) != 0) movk(temp, (imm >> 32) & 0xffff, 32);

[ulan, 2014/03/24 12:45:54]

v8/test/mjsunit and v8/benchmarks did not hit the cases when we omit these
moves. I'd suggest to remove this optimization because it complicates the code
and does not seem to trigger in tests/benchmarks.

+    }
   } else {
     LoadRelocated(temp, Operand(reinterpret_cast<intptr_t>(target), rmode));
   }
   Blr(temp);
 #ifdef DEBUG
   AssertSizeOfCodeGeneratedSince(&start_call, CallSize(target, rmode));
 #endif
 }
 
 
@@ skipping 26 matching lines @@
 }
 
 
 int MacroAssembler::CallSize(Label* target) {
   USE(target);
   return kInstructionSize;
 }
 
 
 int MacroAssembler::CallSize(Address target, RelocInfo::Mode rmode) {
-  USE(target);
-
   // Addresses always have 64 bits, so we shouldn't encounter NONE32.
   ASSERT(rmode != RelocInfo::NONE32);
 
   if (rmode == RelocInfo::NONE64) {
-    return kCallSizeWithoutRelocation;
+    int result = kMaxCallSizeWithoutRelocation;
+    if (!predictable_code_size()) {
+      uint64_t imm = reinterpret_cast<uint64_t>(target);
+      if (((imm >> 16) & 0xffff) == 0) result -= kInstructionSize;
+      if (((imm >> 32) & 0xffff) == 0) result -= kInstructionSize;
+    }
+    return result;
   } else {
     return kCallSizeWithRelocation;
   }
 }
 
 
 int MacroAssembler::CallSize(Handle<Code> code,
                              RelocInfo::Mode rmode,
                              TypeFeedbackId ast_id) {
-  USE(code);
   USE(ast_id);
-
-  // Addresses always have 64 bits, so we shouldn't encounter NONE32.
-  ASSERT(rmode != RelocInfo::NONE32);
-
-  if (rmode == RelocInfo::NONE64) {
-    return kCallSizeWithoutRelocation;
-  } else {
-    return kCallSizeWithRelocation;
-  }
+  AllowDeferredHandleDereference embedding_raw_address;
+  return CallSize(reinterpret_cast<Address>(code.location()), rmode);
 }
 
 
 
 
 
 void MacroAssembler::JumpForHeapNumber(Register object,
                                        Register heap_number_map,
                                        Label* on_heap_number,
                                        Label* on_not_heap_number) {
@@ skipping 3047 matching lines @@
   }
 }
 
 
 #undef __
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM64