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Issue 209923002: ARM64: optimize call immediate (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 9 months ago
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1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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582 ASSERT(instr->IsLdrLiteralX()); 582 ASSERT(instr->IsLdrLiteralX());
583 return candidate; 583 return candidate;
584 } 584 }
585 585
586 586
587 Address Assembler::return_address_from_call_start(Address pc) { 587 Address Assembler::return_address_from_call_start(Address pc) {
588 // The call, generated by MacroAssembler::Call, is one of two possible 588 // The call, generated by MacroAssembler::Call, is one of two possible
589 // sequences: 589 // sequences:
590 // 590 //
591 // Without relocation: 591 // Without relocation:
592 // movz ip0, #(target & 0x000000000000ffff) 592 // movz temp
593 // movk ip0, #(target & 0x00000000ffff0000) 593 // [movk temp] (up to 2 instructions).
594 // movk ip0, #(target & 0x0000ffff00000000) 594 // blr temp
595 // movk ip0, #(target & 0xffff000000000000)
596 // blr ip0
597 // 595 //
598 // With relocation: 596 // With relocation:
599 // ldr ip0, =target 597 // ldr temp, =target
600 // blr ip0 598 // blr temp
601 // 599 //
602 // The return address is immediately after the blr instruction in both cases, 600 // The return address is immediately after the blr instruction in both cases,
603 // so it can be found by adding the call size to the address at the start of 601 // so it can be found by adding the call size to the address at the start of
604 // the call sequence. 602 // the call sequence.
605 STATIC_ASSERT(Assembler::kCallSizeWithoutRelocation == 5 * kInstructionSize);
606 STATIC_ASSERT(Assembler::kCallSizeWithRelocation == 2 * kInstructionSize); 603 STATIC_ASSERT(Assembler::kCallSizeWithRelocation == 2 * kInstructionSize);
607 604
608 Instruction* instr = reinterpret_cast<Instruction*>(pc); 605 Instruction* instr = reinterpret_cast<Instruction*>(pc);
609 if (instr->IsMovz()) { 606 if (instr->IsMovz()) {
607 int movk_count;
608 if (instr->following(1)->IsMovk()) {
609 if (instr->following(2)->IsMovk()) {
610 movk_count = 2;
611 } else {
612 movk_count = 1;
613 }
614 } else {
615 movk_count = 0;
616 }
610 // Verify the instruction sequence. 617 // Verify the instruction sequence.
611 ASSERT(instr->following(1)->IsMovk()); 618 ASSERT(instr->following(movk_count + 1)->IsBranchAndLinkToRegister());
612 ASSERT(instr->following(2)->IsMovk()); 619 return pc + (movk_count + 2) * kInstructionSize;
613 ASSERT(instr->following(3)->IsMovk());
614 ASSERT(instr->following(4)->IsBranchAndLinkToRegister());
615 return pc + Assembler::kCallSizeWithoutRelocation;
616 } else { 620 } else {
617 // Verify the instruction sequence. 621 // Verify the instruction sequence.
618 ASSERT(instr->IsLdrLiteralX()); 622 ASSERT(instr->IsLdrLiteralX());
619 ASSERT(instr->following(1)->IsBranchAndLinkToRegister()); 623 ASSERT(instr->following(1)->IsBranchAndLinkToRegister());
620 return pc + Assembler::kCallSizeWithRelocation; 624 return pc + Assembler::kCallSizeWithRelocation;
621 } 625 }
622 } 626 }
623 627
624 628
625 void Assembler::deserialization_set_special_target_at( 629 void Assembler::deserialization_set_special_target_at(
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1222 1226
1223 1227
1224 void Assembler::ClearRecordedAstId() { 1228 void Assembler::ClearRecordedAstId() {
1225 recorded_ast_id_ = TypeFeedbackId::None(); 1229 recorded_ast_id_ = TypeFeedbackId::None();
1226 } 1230 }
1227 1231
1228 1232
1229 } } // namespace v8::internal 1233 } } // namespace v8::internal
1230 1234
1231 #endif // V8_ARM64_ASSEMBLER_ARM64_INL_H_ 1235 #endif // V8_ARM64_ASSEMBLER_ARM64_INL_H_
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