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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <assert.h> // For assert | 5 #include <assert.h> // For assert |
6 #include <limits.h> // For LONG_MIN, LONG_MAX. | 6 #include <limits.h> // For LONG_MIN, LONG_MAX. |
7 | 7 |
8 #if V8_TARGET_ARCH_S390 | 8 #if V8_TARGET_ARCH_S390 |
9 | 9 |
10 #include "src/base/bits.h" | 10 #include "src/base/bits.h" |
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630 | 630 |
631 return index; | 631 return index; |
632 } | 632 } |
633 | 633 |
634 MemOperand MacroAssembler::SafepointRegisterSlot(Register reg) { | 634 MemOperand MacroAssembler::SafepointRegisterSlot(Register reg) { |
635 return MemOperand(sp, SafepointRegisterStackIndex(reg.code()) * kPointerSize); | 635 return MemOperand(sp, SafepointRegisterStackIndex(reg.code()) * kPointerSize); |
636 } | 636 } |
637 | 637 |
638 MemOperand MacroAssembler::SafepointRegistersAndDoublesSlot(Register reg) { | 638 MemOperand MacroAssembler::SafepointRegistersAndDoublesSlot(Register reg) { |
639 // General purpose registers are pushed last on the stack. | 639 // General purpose registers are pushed last on the stack. |
640 const RegisterConfiguration* config = | 640 const RegisterConfiguration* config = RegisterConfiguration::Crankshaft(); |
641 RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT); | |
642 int doubles_size = config->num_allocatable_double_registers() * kDoubleSize; | 641 int doubles_size = config->num_allocatable_double_registers() * kDoubleSize; |
643 int register_offset = SafepointRegisterStackIndex(reg.code()) * kPointerSize; | 642 int register_offset = SafepointRegisterStackIndex(reg.code()) * kPointerSize; |
644 return MemOperand(sp, doubles_size + register_offset); | 643 return MemOperand(sp, doubles_size + register_offset); |
645 } | 644 } |
646 | 645 |
647 void MacroAssembler::CanonicalizeNaN(const DoubleRegister dst, | 646 void MacroAssembler::CanonicalizeNaN(const DoubleRegister dst, |
648 const DoubleRegister src) { | 647 const DoubleRegister src) { |
649 // Turn potential sNaN into qNaN | 648 // Turn potential sNaN into qNaN |
650 if (!dst.is(src)) ldr(dst, src); | 649 if (!dst.is(src)) ldr(dst, src); |
651 lzdr(kDoubleRegZero); | 650 lzdr(kDoubleRegZero); |
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3690 Register reg4, Register reg5, | 3689 Register reg4, Register reg5, |
3691 Register reg6) { | 3690 Register reg6) { |
3692 RegList regs = 0; | 3691 RegList regs = 0; |
3693 if (reg1.is_valid()) regs |= reg1.bit(); | 3692 if (reg1.is_valid()) regs |= reg1.bit(); |
3694 if (reg2.is_valid()) regs |= reg2.bit(); | 3693 if (reg2.is_valid()) regs |= reg2.bit(); |
3695 if (reg3.is_valid()) regs |= reg3.bit(); | 3694 if (reg3.is_valid()) regs |= reg3.bit(); |
3696 if (reg4.is_valid()) regs |= reg4.bit(); | 3695 if (reg4.is_valid()) regs |= reg4.bit(); |
3697 if (reg5.is_valid()) regs |= reg5.bit(); | 3696 if (reg5.is_valid()) regs |= reg5.bit(); |
3698 if (reg6.is_valid()) regs |= reg6.bit(); | 3697 if (reg6.is_valid()) regs |= reg6.bit(); |
3699 | 3698 |
3700 const RegisterConfiguration* config = | 3699 const RegisterConfiguration* config = RegisterConfiguration::Crankshaft(); |
3701 RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT); | |
3702 for (int i = 0; i < config->num_allocatable_general_registers(); ++i) { | 3700 for (int i = 0; i < config->num_allocatable_general_registers(); ++i) { |
3703 int code = config->GetAllocatableGeneralCode(i); | 3701 int code = config->GetAllocatableGeneralCode(i); |
3704 Register candidate = Register::from_code(code); | 3702 Register candidate = Register::from_code(code); |
3705 if (regs & candidate.bit()) continue; | 3703 if (regs & candidate.bit()) continue; |
3706 return candidate; | 3704 return candidate; |
3707 } | 3705 } |
3708 UNREACHABLE(); | 3706 UNREACHABLE(); |
3709 return no_reg; | 3707 return no_reg; |
3710 } | 3708 } |
3711 | 3709 |
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5517 } | 5515 } |
5518 if (mag.shift > 0) ShiftRightArith(result, result, Operand(mag.shift)); | 5516 if (mag.shift > 0) ShiftRightArith(result, result, Operand(mag.shift)); |
5519 ExtractBit(r0, dividend, 31); | 5517 ExtractBit(r0, dividend, 31); |
5520 AddP(result, r0); | 5518 AddP(result, r0); |
5521 } | 5519 } |
5522 | 5520 |
5523 } // namespace internal | 5521 } // namespace internal |
5524 } // namespace v8 | 5522 } // namespace v8 |
5525 | 5523 |
5526 #endif // V8_TARGET_ARCH_S390 | 5524 #endif // V8_TARGET_ARCH_S390 |
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