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Side by Side Diff: src/register-configuration.h

Issue 2092413002: [RegisterConfiguration] Streamline access to arch defaults, simplify Registers. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Fix compile. Created 4 years, 5 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_REGISTER_CONFIGURATION_H_ 5 #ifndef V8_COMPILER_REGISTER_CONFIGURATION_H_
6 #define V8_COMPILER_REGISTER_CONFIGURATION_H_ 6 #define V8_COMPILER_REGISTER_CONFIGURATION_H_
7 7
8 #include "src/base/macros.h" 8 #include "src/base/macros.h"
9 #include "src/machine-type.h" 9 #include "src/machine-type.h"
10 10
11 namespace v8 { 11 namespace v8 {
12 namespace internal { 12 namespace internal {
13 13
14 // An architecture independent representation of the sets of registers available 14 // An architecture independent representation of the sets of registers available
15 // for instruction creation. 15 // for instruction creation.
16 class RegisterConfiguration { 16 class RegisterConfiguration {
17 public: 17 public:
18 // Define the optimized compiler selector for register configuration
19 // selection.
20 //
21 // TODO(X87): This distinction in RegisterConfigurations is temporary
22 // until x87 TF supports all of the registers that Crankshaft does.
23 enum CompilerSelector { CRANKSHAFT, TURBOFAN };
24
25 enum AliasingKind { 18 enum AliasingKind {
26 // Registers alias a single register of every other size (e.g. Intel). 19 // Registers alias a single register of every other size (e.g. Intel).
27 OVERLAP, 20 OVERLAP,
28 // Registers alias two registers of the next smaller size (e.g. ARM). 21 // Registers alias two registers of the next smaller size (e.g. ARM).
29 COMBINE 22 COMBINE
30 }; 23 };
31 24
32 // Architecture independent maxes. 25 // Architecture independent maxes.
33 static const int kMaxGeneralRegisters = 32; 26 static const int kMaxGeneralRegisters = 32;
34 static const int kMaxFPRegisters = 32; 27 static const int kMaxFPRegisters = 32;
35 28
36 static const RegisterConfiguration* ArchDefault(CompilerSelector compiler); 29 // Default RegisterConfigurations for the target architecture.
30 // TODO(X87): This distinction in RegisterConfigurations is temporary
31 // until x87 TF supports all of the registers that Crankshaft does.
32 static const RegisterConfiguration* Crankshaft();
33 static const RegisterConfiguration* Turbofan();
37 34
38 RegisterConfiguration(int num_general_registers, int num_double_registers, 35 RegisterConfiguration(int num_general_registers, int num_double_registers,
39 int num_allocatable_general_registers, 36 int num_allocatable_general_registers,
40 int num_allocatable_double_registers, 37 int num_allocatable_double_registers,
41 const int* allocatable_general_codes, 38 const int* allocatable_general_codes,
42 const int* allocatable_double_codes, 39 const int* allocatable_double_codes,
43 AliasingKind fp_aliasing_kind, 40 AliasingKind fp_aliasing_kind,
44 char const* const* general_names, 41 char const* const* general_names,
45 char const* const* float_names, 42 char const* const* float_names,
46 char const* const* double_names); 43 char const* const* double_names);
(...skipping 13 matching lines...) Expand all
60 AliasingKind fp_aliasing_kind() const { return fp_aliasing_kind_; } 57 AliasingKind fp_aliasing_kind() const { return fp_aliasing_kind_; }
61 int32_t allocatable_general_codes_mask() const { 58 int32_t allocatable_general_codes_mask() const {
62 return allocatable_general_codes_mask_; 59 return allocatable_general_codes_mask_;
63 } 60 }
64 int32_t allocatable_double_codes_mask() const { 61 int32_t allocatable_double_codes_mask() const {
65 return allocatable_double_codes_mask_; 62 return allocatable_double_codes_mask_;
66 } 63 }
67 int GetAllocatableGeneralCode(int index) const { 64 int GetAllocatableGeneralCode(int index) const {
68 return allocatable_general_codes_[index]; 65 return allocatable_general_codes_[index];
69 } 66 }
67 bool IsAllocatableGeneralCode(int index) const {
68 return ((1 << index) & allocatable_general_codes_mask_) != 0;
69 }
70 int GetAllocatableDoubleCode(int index) const { 70 int GetAllocatableDoubleCode(int index) const {
71 return allocatable_double_codes_[index]; 71 return allocatable_double_codes_[index];
72 } 72 }
73 bool IsAllocatableDoubleCode(int index) const {
74 return ((1 << index) & allocatable_double_codes_mask_) != 0;
75 }
73 int GetAllocatableFloatCode(int index) const { 76 int GetAllocatableFloatCode(int index) const {
74 return allocatable_float_codes_[index]; 77 return allocatable_float_codes_[index];
75 } 78 }
79 bool IsAllocatableFloatCode(int index) const {
80 return ((1 << index) & allocatable_float_codes_mask_) != 0;
81 }
76 const char* GetGeneralRegisterName(int code) const { 82 const char* GetGeneralRegisterName(int code) const {
77 return general_register_names_[code]; 83 return general_register_names_[code];
78 } 84 }
79 const char* GetFloatRegisterName(int code) const { 85 const char* GetFloatRegisterName(int code) const {
80 return float_register_names_[code]; 86 return float_register_names_[code];
81 } 87 }
82 const char* GetDoubleRegisterName(int code) const { 88 const char* GetDoubleRegisterName(int code) const {
83 return double_register_names_[code]; 89 return double_register_names_[code];
84 } 90 }
85 const int* allocatable_general_codes() const { 91 const int* allocatable_general_codes() const {
(...skipping 20 matching lines...) Expand all
106 112
107 private: 113 private:
108 const int num_general_registers_; 114 const int num_general_registers_;
109 int num_float_registers_; 115 int num_float_registers_;
110 const int num_double_registers_; 116 const int num_double_registers_;
111 int num_allocatable_general_registers_; 117 int num_allocatable_general_registers_;
112 int num_allocatable_double_registers_; 118 int num_allocatable_double_registers_;
113 int num_allocatable_float_registers_; 119 int num_allocatable_float_registers_;
114 int32_t allocatable_general_codes_mask_; 120 int32_t allocatable_general_codes_mask_;
115 int32_t allocatable_double_codes_mask_; 121 int32_t allocatable_double_codes_mask_;
122 int32_t allocatable_float_codes_mask_;
116 const int* allocatable_general_codes_; 123 const int* allocatable_general_codes_;
117 const int* allocatable_double_codes_; 124 const int* allocatable_double_codes_;
118 int allocatable_float_codes_[kMaxFPRegisters]; 125 int allocatable_float_codes_[kMaxFPRegisters];
119 AliasingKind fp_aliasing_kind_; 126 AliasingKind fp_aliasing_kind_;
120 char const* const* general_register_names_; 127 char const* const* general_register_names_;
121 char const* const* float_register_names_; 128 char const* const* float_register_names_;
122 char const* const* double_register_names_; 129 char const* const* double_register_names_;
123 }; 130 };
124 131
125 } // namespace internal 132 } // namespace internal
126 } // namespace v8 133 } // namespace v8
127 134
128 #endif // V8_COMPILER_REGISTER_CONFIGURATION_H_ 135 #endif // V8_COMPILER_REGISTER_CONFIGURATION_H_
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