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| 1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #include <assert.h> // For assert | 5 #include <assert.h> // For assert |
| 6 #include <limits.h> // For LONG_MIN, LONG_MAX. | 6 #include <limits.h> // For LONG_MIN, LONG_MAX. |
| 7 | 7 |
| 8 #if V8_TARGET_ARCH_PPC | 8 #if V8_TARGET_ARCH_PPC |
| 9 | 9 |
| 10 #include "src/base/bits.h" | 10 #include "src/base/bits.h" |
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| 709 } | 709 } |
| 710 | 710 |
| 711 | 711 |
| 712 MemOperand MacroAssembler::SafepointRegisterSlot(Register reg) { | 712 MemOperand MacroAssembler::SafepointRegisterSlot(Register reg) { |
| 713 return MemOperand(sp, SafepointRegisterStackIndex(reg.code()) * kPointerSize); | 713 return MemOperand(sp, SafepointRegisterStackIndex(reg.code()) * kPointerSize); |
| 714 } | 714 } |
| 715 | 715 |
| 716 | 716 |
| 717 MemOperand MacroAssembler::SafepointRegistersAndDoublesSlot(Register reg) { | 717 MemOperand MacroAssembler::SafepointRegistersAndDoublesSlot(Register reg) { |
| 718 // General purpose registers are pushed last on the stack. | 718 // General purpose registers are pushed last on the stack. |
| 719 const RegisterConfiguration* config = | 719 const RegisterConfiguration* config = RegisterConfiguration::Crankshaft(); |
| 720 RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT); | |
| 721 int doubles_size = config->num_allocatable_double_registers() * kDoubleSize; | 720 int doubles_size = config->num_allocatable_double_registers() * kDoubleSize; |
| 722 int register_offset = SafepointRegisterStackIndex(reg.code()) * kPointerSize; | 721 int register_offset = SafepointRegisterStackIndex(reg.code()) * kPointerSize; |
| 723 return MemOperand(sp, doubles_size + register_offset); | 722 return MemOperand(sp, doubles_size + register_offset); |
| 724 } | 723 } |
| 725 | 724 |
| 726 | 725 |
| 727 void MacroAssembler::CanonicalizeNaN(const DoubleRegister dst, | 726 void MacroAssembler::CanonicalizeNaN(const DoubleRegister dst, |
| 728 const DoubleRegister src) { | 727 const DoubleRegister src) { |
| 729 // Turn potential sNaN into qNaN. | 728 // Turn potential sNaN into qNaN. |
| 730 fsub(dst, src, kDoubleRegZero); | 729 fsub(dst, src, kDoubleRegZero); |
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| 4735 Register reg4, Register reg5, | 4734 Register reg4, Register reg5, |
| 4736 Register reg6) { | 4735 Register reg6) { |
| 4737 RegList regs = 0; | 4736 RegList regs = 0; |
| 4738 if (reg1.is_valid()) regs |= reg1.bit(); | 4737 if (reg1.is_valid()) regs |= reg1.bit(); |
| 4739 if (reg2.is_valid()) regs |= reg2.bit(); | 4738 if (reg2.is_valid()) regs |= reg2.bit(); |
| 4740 if (reg3.is_valid()) regs |= reg3.bit(); | 4739 if (reg3.is_valid()) regs |= reg3.bit(); |
| 4741 if (reg4.is_valid()) regs |= reg4.bit(); | 4740 if (reg4.is_valid()) regs |= reg4.bit(); |
| 4742 if (reg5.is_valid()) regs |= reg5.bit(); | 4741 if (reg5.is_valid()) regs |= reg5.bit(); |
| 4743 if (reg6.is_valid()) regs |= reg6.bit(); | 4742 if (reg6.is_valid()) regs |= reg6.bit(); |
| 4744 | 4743 |
| 4745 const RegisterConfiguration* config = | 4744 const RegisterConfiguration* config = RegisterConfiguration::Crankshaft(); |
| 4746 RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT); | |
| 4747 for (int i = 0; i < config->num_allocatable_general_registers(); ++i) { | 4745 for (int i = 0; i < config->num_allocatable_general_registers(); ++i) { |
| 4748 int code = config->GetAllocatableGeneralCode(i); | 4746 int code = config->GetAllocatableGeneralCode(i); |
| 4749 Register candidate = Register::from_code(code); | 4747 Register candidate = Register::from_code(code); |
| 4750 if (regs & candidate.bit()) continue; | 4748 if (regs & candidate.bit()) continue; |
| 4751 return candidate; | 4749 return candidate; |
| 4752 } | 4750 } |
| 4753 UNREACHABLE(); | 4751 UNREACHABLE(); |
| 4754 return no_reg; | 4752 return no_reg; |
| 4755 } | 4753 } |
| 4756 | 4754 |
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| 4881 } | 4879 } |
| 4882 if (mag.shift > 0) srawi(result, result, mag.shift); | 4880 if (mag.shift > 0) srawi(result, result, mag.shift); |
| 4883 ExtractBit(r0, dividend, 31); | 4881 ExtractBit(r0, dividend, 31); |
| 4884 add(result, result, r0); | 4882 add(result, result, r0); |
| 4885 } | 4883 } |
| 4886 | 4884 |
| 4887 } // namespace internal | 4885 } // namespace internal |
| 4888 } // namespace v8 | 4886 } // namespace v8 |
| 4889 | 4887 |
| 4890 #endif // V8_TARGET_ARCH_PPC | 4888 #endif // V8_TARGET_ARCH_PPC |
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