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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include "src/compiler/common-operator.h" | 5 #include "src/compiler/common-operator.h" |
6 #include "src/compiler/graph.h" | 6 #include "src/compiler/graph.h" |
7 #include "src/compiler/instruction.h" | 7 #include "src/compiler/instruction.h" |
8 #include "src/compiler/schedule.h" | 8 #include "src/compiler/schedule.h" |
9 #include "src/compiler/state-values-utils.h" | 9 #include "src/compiler/state-values-utils.h" |
10 | 10 |
11 namespace v8 { | 11 namespace v8 { |
12 namespace internal { | 12 namespace internal { |
13 namespace compiler { | 13 namespace compiler { |
14 | 14 |
| 15 const auto GetRegConfig = RegisterConfiguration::Turbofan; |
15 | 16 |
16 FlagsCondition CommuteFlagsCondition(FlagsCondition condition) { | 17 FlagsCondition CommuteFlagsCondition(FlagsCondition condition) { |
17 switch (condition) { | 18 switch (condition) { |
18 case kSignedLessThan: | 19 case kSignedLessThan: |
19 return kSignedGreaterThan; | 20 return kSignedGreaterThan; |
20 case kSignedGreaterThanOrEqual: | 21 case kSignedGreaterThanOrEqual: |
21 return kSignedLessThanOrEqual; | 22 return kSignedLessThanOrEqual; |
22 case kSignedLessThanOrEqual: | 23 case kSignedLessThanOrEqual: |
23 return kSignedGreaterThanOrEqual; | 24 return kSignedGreaterThanOrEqual; |
24 case kSignedGreaterThan: | 25 case kSignedGreaterThan: |
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57 } | 58 } |
58 UNREACHABLE(); | 59 UNREACHABLE(); |
59 return condition; | 60 return condition; |
60 } | 61 } |
61 | 62 |
62 bool InstructionOperand::InterferesWith(const InstructionOperand& that) const { | 63 bool InstructionOperand::InterferesWith(const InstructionOperand& that) const { |
63 if (!IsFPRegister() || !that.IsFPRegister()) return EqualsCanonicalized(that); | 64 if (!IsFPRegister() || !that.IsFPRegister()) return EqualsCanonicalized(that); |
64 | 65 |
65 const LocationOperand& loc1 = *LocationOperand::cast(this); | 66 const LocationOperand& loc1 = *LocationOperand::cast(this); |
66 const LocationOperand& loc2 = LocationOperand::cast(that); | 67 const LocationOperand& loc2 = LocationOperand::cast(that); |
67 const RegisterConfiguration* config = | 68 const RegisterConfiguration* config = GetRegConfig(); |
68 RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN); | |
69 if (config->fp_aliasing_kind() != RegisterConfiguration::COMBINE) | 69 if (config->fp_aliasing_kind() != RegisterConfiguration::COMBINE) |
70 return loc1.register_code() == loc2.register_code(); | 70 return loc1.register_code() == loc2.register_code(); |
71 | 71 |
72 return config->AreAliases(loc1.representation(), loc1.register_code(), | 72 return config->AreAliases(loc1.representation(), loc1.register_code(), |
73 loc2.representation(), loc2.register_code()); | 73 loc2.representation(), loc2.register_code()); |
74 } | 74 } |
75 | 75 |
76 void InstructionOperand::Print(const RegisterConfiguration* config) const { | 76 void InstructionOperand::Print(const RegisterConfiguration* config) const { |
77 OFStream os(stdout); | 77 OFStream os(stdout); |
78 PrintableInstructionOperand wrapper; | 78 PrintableInstructionOperand wrapper; |
79 wrapper.register_configuration_ = config; | 79 wrapper.register_configuration_ = config; |
80 wrapper.op_ = *this; | 80 wrapper.op_ = *this; |
81 os << wrapper << std::endl; | 81 os << wrapper << std::endl; |
82 } | 82 } |
83 | 83 |
84 | 84 void InstructionOperand::Print() const { Print(GetRegConfig()); } |
85 void InstructionOperand::Print() const { | |
86 const RegisterConfiguration* config = | |
87 RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN); | |
88 Print(config); | |
89 } | |
90 | 85 |
91 std::ostream& operator<<(std::ostream& os, | 86 std::ostream& operator<<(std::ostream& os, |
92 const PrintableInstructionOperand& printable) { | 87 const PrintableInstructionOperand& printable) { |
93 const InstructionOperand& op = printable.op_; | 88 const InstructionOperand& op = printable.op_; |
94 const RegisterConfiguration* conf = printable.register_configuration_; | 89 const RegisterConfiguration* conf = printable.register_configuration_; |
95 switch (op.kind()) { | 90 switch (op.kind()) { |
96 case InstructionOperand::UNALLOCATED: { | 91 case InstructionOperand::UNALLOCATED: { |
97 const UnallocatedOperand* unalloc = UnallocatedOperand::cast(&op); | 92 const UnallocatedOperand* unalloc = UnallocatedOperand::cast(&op); |
98 os << "v" << unalloc->virtual_register(); | 93 os << "v" << unalloc->virtual_register(); |
99 if (unalloc->basic_policy() == UnallocatedOperand::FIXED_SLOT) { | 94 if (unalloc->basic_policy() == UnallocatedOperand::FIXED_SLOT) { |
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135 } | 130 } |
136 } | 131 } |
137 case InstructionOperand::EXPLICIT: | 132 case InstructionOperand::EXPLICIT: |
138 case InstructionOperand::ALLOCATED: { | 133 case InstructionOperand::ALLOCATED: { |
139 LocationOperand allocated = LocationOperand::cast(op); | 134 LocationOperand allocated = LocationOperand::cast(op); |
140 if (op.IsStackSlot()) { | 135 if (op.IsStackSlot()) { |
141 os << "[stack:" << allocated.index(); | 136 os << "[stack:" << allocated.index(); |
142 } else if (op.IsFPStackSlot()) { | 137 } else if (op.IsFPStackSlot()) { |
143 os << "[fp_stack:" << allocated.index(); | 138 os << "[fp_stack:" << allocated.index(); |
144 } else if (op.IsRegister()) { | 139 } else if (op.IsRegister()) { |
145 os << "[" << allocated.GetRegister().ToString() << "|R"; | 140 os << "[" |
| 141 << GetRegConfig()->GetGeneralRegisterName(allocated.register_code()) |
| 142 << "|R"; |
146 } else if (op.IsDoubleRegister()) { | 143 } else if (op.IsDoubleRegister()) { |
147 os << "[" << allocated.GetDoubleRegister().ToString() << "|R"; | 144 os << "[" |
| 145 << GetRegConfig()->GetDoubleRegisterName(allocated.register_code()) |
| 146 << "|R"; |
148 } else { | 147 } else { |
149 DCHECK(op.IsFloatRegister()); | 148 DCHECK(op.IsFloatRegister()); |
150 os << "[" << allocated.GetFloatRegister().ToString() << "|R"; | 149 os << "[" |
| 150 << GetRegConfig()->GetFloatRegisterName(allocated.register_code()) |
| 151 << "|R"; |
151 } | 152 } |
152 if (allocated.IsExplicit()) { | 153 if (allocated.IsExplicit()) { |
153 os << "|E"; | 154 os << "|E"; |
154 } | 155 } |
155 switch (allocated.representation()) { | 156 switch (allocated.representation()) { |
156 case MachineRepresentation::kNone: | 157 case MachineRepresentation::kNone: |
157 os << "|-"; | 158 os << "|-"; |
158 break; | 159 break; |
159 case MachineRepresentation::kBit: | 160 case MachineRepresentation::kBit: |
160 os << "|b"; | 161 os << "|b"; |
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196 void MoveOperands::Print(const RegisterConfiguration* config) const { | 197 void MoveOperands::Print(const RegisterConfiguration* config) const { |
197 OFStream os(stdout); | 198 OFStream os(stdout); |
198 PrintableInstructionOperand wrapper; | 199 PrintableInstructionOperand wrapper; |
199 wrapper.register_configuration_ = config; | 200 wrapper.register_configuration_ = config; |
200 wrapper.op_ = destination(); | 201 wrapper.op_ = destination(); |
201 os << wrapper << " = "; | 202 os << wrapper << " = "; |
202 wrapper.op_ = source(); | 203 wrapper.op_ = source(); |
203 os << wrapper << std::endl; | 204 os << wrapper << std::endl; |
204 } | 205 } |
205 | 206 |
206 | 207 void MoveOperands::Print() const { Print(GetRegConfig()); } |
207 void MoveOperands::Print() const { | |
208 const RegisterConfiguration* config = | |
209 RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN); | |
210 Print(config); | |
211 } | |
212 | |
213 | 208 |
214 std::ostream& operator<<(std::ostream& os, | 209 std::ostream& operator<<(std::ostream& os, |
215 const PrintableMoveOperands& printable) { | 210 const PrintableMoveOperands& printable) { |
216 const MoveOperands& mo = *printable.move_operands_; | 211 const MoveOperands& mo = *printable.move_operands_; |
217 PrintableInstructionOperand printable_op = {printable.register_configuration_, | 212 PrintableInstructionOperand printable_op = {printable.register_configuration_, |
218 mo.destination()}; | 213 mo.destination()}; |
219 os << printable_op; | 214 os << printable_op; |
220 if (!mo.source().Equals(mo.destination())) { | 215 if (!mo.source().Equals(mo.destination())) { |
221 printable_op.op_ = mo.source(); | 216 printable_op.op_ = mo.source(); |
222 os << " = " << printable_op; | 217 os << " = " << printable_op; |
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251 DCHECK_IMPLIES(replacement == to_eliminate, replacement == nullptr); | 246 DCHECK_IMPLIES(replacement == to_eliminate, replacement == nullptr); |
252 if (replacement != nullptr) move->set_source(replacement->source()); | 247 if (replacement != nullptr) move->set_source(replacement->source()); |
253 return to_eliminate; | 248 return to_eliminate; |
254 } | 249 } |
255 | 250 |
256 | 251 |
257 ExplicitOperand::ExplicitOperand(LocationKind kind, MachineRepresentation rep, | 252 ExplicitOperand::ExplicitOperand(LocationKind kind, MachineRepresentation rep, |
258 int index) | 253 int index) |
259 : LocationOperand(EXPLICIT, kind, rep, index) { | 254 : LocationOperand(EXPLICIT, kind, rep, index) { |
260 DCHECK_IMPLIES(kind == REGISTER && !IsFloatingPoint(rep), | 255 DCHECK_IMPLIES(kind == REGISTER && !IsFloatingPoint(rep), |
261 Register::from_code(index).IsAllocatable( | 256 GetRegConfig()->IsAllocatableGeneralCode(index)); |
262 RegisterConfiguration::TURBOFAN)); | |
263 DCHECK_IMPLIES(kind == REGISTER && rep == MachineRepresentation::kFloat32, | 257 DCHECK_IMPLIES(kind == REGISTER && rep == MachineRepresentation::kFloat32, |
264 FloatRegister::from_code(index).IsAllocatable( | 258 GetRegConfig()->IsAllocatableFloatCode(index)); |
265 RegisterConfiguration::TURBOFAN)); | |
266 DCHECK_IMPLIES(kind == REGISTER && (rep == MachineRepresentation::kFloat64), | 259 DCHECK_IMPLIES(kind == REGISTER && (rep == MachineRepresentation::kFloat64), |
267 DoubleRegister::from_code(index).IsAllocatable( | 260 GetRegConfig()->IsAllocatableDoubleCode(index)); |
268 RegisterConfiguration::TURBOFAN)); | |
269 } | 261 } |
270 | 262 |
271 Instruction::Instruction(InstructionCode opcode) | 263 Instruction::Instruction(InstructionCode opcode) |
272 : opcode_(opcode), | 264 : opcode_(opcode), |
273 bit_field_(OutputCountField::encode(0) | InputCountField::encode(0) | | 265 bit_field_(OutputCountField::encode(0) | InputCountField::encode(0) | |
274 TempCountField::encode(0) | IsCallField::encode(false)), | 266 TempCountField::encode(0) | IsCallField::encode(false)), |
275 reference_map_(nullptr), | 267 reference_map_(nullptr), |
276 block_(nullptr) { | 268 block_(nullptr) { |
277 parallel_moves_[0] = nullptr; | 269 parallel_moves_[0] = nullptr; |
278 parallel_moves_[1] = nullptr; | 270 parallel_moves_[1] = nullptr; |
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319 | 311 |
320 | 312 |
321 void Instruction::Print(const RegisterConfiguration* config) const { | 313 void Instruction::Print(const RegisterConfiguration* config) const { |
322 OFStream os(stdout); | 314 OFStream os(stdout); |
323 PrintableInstruction wrapper; | 315 PrintableInstruction wrapper; |
324 wrapper.instr_ = this; | 316 wrapper.instr_ = this; |
325 wrapper.register_configuration_ = config; | 317 wrapper.register_configuration_ = config; |
326 os << wrapper << std::endl; | 318 os << wrapper << std::endl; |
327 } | 319 } |
328 | 320 |
329 | 321 void Instruction::Print() const { Print(GetRegConfig()); } |
330 void Instruction::Print() const { | |
331 const RegisterConfiguration* config = | |
332 RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN); | |
333 Print(config); | |
334 } | |
335 | |
336 | 322 |
337 std::ostream& operator<<(std::ostream& os, | 323 std::ostream& operator<<(std::ostream& os, |
338 const PrintableParallelMove& printable) { | 324 const PrintableParallelMove& printable) { |
339 const ParallelMove& pm = *printable.parallel_move_; | 325 const ParallelMove& pm = *printable.parallel_move_; |
340 bool first = true; | 326 bool first = true; |
341 for (MoveOperands* move : pm) { | 327 for (MoveOperands* move : pm) { |
342 if (move->IsEliminated()) continue; | 328 if (move->IsEliminated()) continue; |
343 if (!first) os << " "; | 329 if (!first) os << " "; |
344 first = false; | 330 first = false; |
345 PrintableMoveOperands pmo = {printable.register_configuration_, move}; | 331 PrintableMoveOperands pmo = {printable.register_configuration_, move}; |
346 os << pmo; | 332 os << pmo; |
347 } | 333 } |
348 return os; | 334 return os; |
349 } | 335 } |
350 | 336 |
351 | 337 |
352 void ReferenceMap::RecordReference(const AllocatedOperand& op) { | 338 void ReferenceMap::RecordReference(const AllocatedOperand& op) { |
353 // Do not record arguments as pointers. | 339 // Do not record arguments as pointers. |
354 if (op.IsStackSlot() && LocationOperand::cast(op).index() < 0) return; | 340 if (op.IsStackSlot() && LocationOperand::cast(op).index() < 0) return; |
355 DCHECK(!op.IsFPRegister() && !op.IsFPStackSlot()); | 341 DCHECK(!op.IsFPRegister() && !op.IsFPStackSlot()); |
356 reference_operands_.push_back(op); | 342 reference_operands_.push_back(op); |
357 } | 343 } |
358 | 344 |
359 | 345 |
360 std::ostream& operator<<(std::ostream& os, const ReferenceMap& pm) { | 346 std::ostream& operator<<(std::ostream& os, const ReferenceMap& pm) { |
361 os << "{"; | 347 os << "{"; |
362 bool first = true; | 348 bool first = true; |
363 PrintableInstructionOperand poi = { | 349 PrintableInstructionOperand poi = {GetRegConfig(), InstructionOperand()}; |
364 RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN), | |
365 InstructionOperand()}; | |
366 for (const InstructionOperand& op : pm.reference_operands_) { | 350 for (const InstructionOperand& op : pm.reference_operands_) { |
367 if (!first) { | 351 if (!first) { |
368 os << ";"; | 352 os << ";"; |
369 } else { | 353 } else { |
370 first = false; | 354 first = false; |
371 } | 355 } |
372 poi.op_ = op; | 356 poi.op_ = op; |
373 os << poi; | 357 os << poi; |
374 } | 358 } |
375 return os << "}"; | 359 return os << "}"; |
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890 | 874 |
891 | 875 |
892 void InstructionSequence::Print(const RegisterConfiguration* config) const { | 876 void InstructionSequence::Print(const RegisterConfiguration* config) const { |
893 OFStream os(stdout); | 877 OFStream os(stdout); |
894 PrintableInstructionSequence wrapper; | 878 PrintableInstructionSequence wrapper; |
895 wrapper.register_configuration_ = config; | 879 wrapper.register_configuration_ = config; |
896 wrapper.sequence_ = this; | 880 wrapper.sequence_ = this; |
897 os << wrapper << std::endl; | 881 os << wrapper << std::endl; |
898 } | 882 } |
899 | 883 |
900 | 884 void InstructionSequence::Print() const { Print(GetRegConfig()); } |
901 void InstructionSequence::Print() const { | |
902 const RegisterConfiguration* config = | |
903 RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN); | |
904 Print(config); | |
905 } | |
906 | 885 |
907 void InstructionSequence::PrintBlock(const RegisterConfiguration* config, | 886 void InstructionSequence::PrintBlock(const RegisterConfiguration* config, |
908 int block_id) const { | 887 int block_id) const { |
909 OFStream os(stdout); | 888 OFStream os(stdout); |
910 RpoNumber rpo = RpoNumber::FromInt(block_id); | 889 RpoNumber rpo = RpoNumber::FromInt(block_id); |
911 const InstructionBlock* block = InstructionBlockAt(rpo); | 890 const InstructionBlock* block = InstructionBlockAt(rpo); |
912 CHECK(block->rpo_number() == rpo); | 891 CHECK(block->rpo_number() == rpo); |
913 | 892 |
914 os << "B" << block->rpo_number(); | 893 os << "B" << block->rpo_number(); |
915 os << ": AO#" << block->ao_number(); | 894 os << ": AO#" << block->ao_number(); |
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949 os << " " << buf.start() << ": " << printable_instr << "\n"; | 928 os << " " << buf.start() << ": " << printable_instr << "\n"; |
950 } | 929 } |
951 | 930 |
952 for (RpoNumber succ : block->successors()) { | 931 for (RpoNumber succ : block->successors()) { |
953 os << " B" << succ.ToInt(); | 932 os << " B" << succ.ToInt(); |
954 } | 933 } |
955 os << "\n"; | 934 os << "\n"; |
956 } | 935 } |
957 | 936 |
958 void InstructionSequence::PrintBlock(int block_id) const { | 937 void InstructionSequence::PrintBlock(int block_id) const { |
959 const RegisterConfiguration* config = | 938 PrintBlock(GetRegConfig(), block_id); |
960 RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN); | |
961 PrintBlock(config, block_id); | |
962 } | 939 } |
963 | 940 |
964 FrameStateDescriptor::FrameStateDescriptor( | 941 FrameStateDescriptor::FrameStateDescriptor( |
965 Zone* zone, FrameStateType type, BailoutId bailout_id, | 942 Zone* zone, FrameStateType type, BailoutId bailout_id, |
966 OutputFrameStateCombine state_combine, size_t parameters_count, | 943 OutputFrameStateCombine state_combine, size_t parameters_count, |
967 size_t locals_count, size_t stack_count, | 944 size_t locals_count, size_t stack_count, |
968 MaybeHandle<SharedFunctionInfo> shared_info, | 945 MaybeHandle<SharedFunctionInfo> shared_info, |
969 FrameStateDescriptor* outer_state) | 946 FrameStateDescriptor* outer_state) |
970 : type_(type), | 947 : type_(type), |
971 bailout_id_(bailout_id), | 948 bailout_id_(bailout_id), |
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1043 } | 1020 } |
1044 for (int i = 0; i < code.InstructionBlockCount(); i++) { | 1021 for (int i = 0; i < code.InstructionBlockCount(); i++) { |
1045 printable.sequence_->PrintBlock(printable.register_configuration_, i); | 1022 printable.sequence_->PrintBlock(printable.register_configuration_, i); |
1046 } | 1023 } |
1047 return os; | 1024 return os; |
1048 } | 1025 } |
1049 | 1026 |
1050 } // namespace compiler | 1027 } // namespace compiler |
1051 } // namespace internal | 1028 } // namespace internal |
1052 } // namespace v8 | 1029 } // namespace v8 |
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