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Side by Side Diff: src/register-configuration.h

Issue 2092103004: [Turbofan] Add Simd128 registers to RegisterConfiguration. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Eliminate some dead code, simplify. Created 4 years, 5 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_REGISTER_CONFIGURATION_H_ 5 #ifndef V8_COMPILER_REGISTER_CONFIGURATION_H_
6 #define V8_COMPILER_REGISTER_CONFIGURATION_H_ 6 #define V8_COMPILER_REGISTER_CONFIGURATION_H_
7 7
8 #include "src/base/macros.h" 8 #include "src/base/macros.h"
9 #include "src/machine-type.h" 9 #include "src/machine-type.h"
10 10
(...skipping 22 matching lines...) Expand all
33 static const RegisterConfiguration* Turbofan(); 33 static const RegisterConfiguration* Turbofan();
34 34
35 RegisterConfiguration(int num_general_registers, int num_double_registers, 35 RegisterConfiguration(int num_general_registers, int num_double_registers,
36 int num_allocatable_general_registers, 36 int num_allocatable_general_registers,
37 int num_allocatable_double_registers, 37 int num_allocatable_double_registers,
38 const int* allocatable_general_codes, 38 const int* allocatable_general_codes,
39 const int* allocatable_double_codes, 39 const int* allocatable_double_codes,
40 AliasingKind fp_aliasing_kind, 40 AliasingKind fp_aliasing_kind,
41 char const* const* general_names, 41 char const* const* general_names,
42 char const* const* float_names, 42 char const* const* float_names,
43 char const* const* double_names); 43 char const* const* double_names,
44 char const* const* simd128_names);
44 45
45 int num_general_registers() const { return num_general_registers_; } 46 int num_general_registers() const { return num_general_registers_; }
46 int num_float_registers() const { return num_float_registers_; } 47 int num_float_registers() const { return num_float_registers_; }
47 int num_double_registers() const { return num_double_registers_; } 48 int num_double_registers() const { return num_double_registers_; }
49 int num_simd128_registers() const { return num_simd128_registers_; }
48 int num_allocatable_general_registers() const { 50 int num_allocatable_general_registers() const {
49 return num_allocatable_general_registers_; 51 return num_allocatable_general_registers_;
50 } 52 }
53 int num_allocatable_float_registers() const {
54 return num_allocatable_float_registers_;
55 }
51 int num_allocatable_double_registers() const { 56 int num_allocatable_double_registers() const {
52 return num_allocatable_double_registers_; 57 return num_allocatable_double_registers_;
53 } 58 }
54 int num_allocatable_float_registers() const { 59 int num_allocatable_simd128_registers() const {
55 return num_allocatable_float_registers_; 60 return num_allocatable_simd128_registers_;
56 } 61 }
57 AliasingKind fp_aliasing_kind() const { return fp_aliasing_kind_; } 62 AliasingKind fp_aliasing_kind() const { return fp_aliasing_kind_; }
58 int32_t allocatable_general_codes_mask() const { 63 int32_t allocatable_general_codes_mask() const {
59 return allocatable_general_codes_mask_; 64 return allocatable_general_codes_mask_;
60 } 65 }
61 int32_t allocatable_double_codes_mask() const { 66 int32_t allocatable_double_codes_mask() const {
62 return allocatable_double_codes_mask_; 67 return allocatable_double_codes_mask_;
63 } 68 }
64 int GetAllocatableGeneralCode(int index) const { 69 int GetAllocatableGeneralCode(int index) const {
65 return allocatable_general_codes_[index]; 70 return allocatable_general_codes_[index];
66 } 71 }
67 bool IsAllocatableGeneralCode(int index) const { 72 bool IsAllocatableGeneralCode(int index) const {
68 return ((1 << index) & allocatable_general_codes_mask_) != 0; 73 return ((1 << index) & allocatable_general_codes_mask_) != 0;
69 } 74 }
75 int GetAllocatableFloatCode(int index) const {
76 return allocatable_float_codes_[index];
77 }
78 bool IsAllocatableFloatCode(int index) const {
79 return ((1 << index) & allocatable_float_codes_mask_) != 0;
80 }
70 int GetAllocatableDoubleCode(int index) const { 81 int GetAllocatableDoubleCode(int index) const {
71 return allocatable_double_codes_[index]; 82 return allocatable_double_codes_[index];
72 } 83 }
73 bool IsAllocatableDoubleCode(int index) const { 84 bool IsAllocatableDoubleCode(int index) const {
74 return ((1 << index) & allocatable_double_codes_mask_) != 0; 85 return ((1 << index) & allocatable_double_codes_mask_) != 0;
75 } 86 }
76 int GetAllocatableFloatCode(int index) const { 87 int GetAllocatableSimd128Code(int index) const {
77 return allocatable_float_codes_[index]; 88 return allocatable_simd128_codes_[index];
78 } 89 }
79 bool IsAllocatableFloatCode(int index) const { 90 bool IsAllocatableSimd128Code(int index) const {
80 return ((1 << index) & allocatable_float_codes_mask_) != 0; 91 return ((1 << index) & allocatable_simd128_codes_mask_) != 0;
81 } 92 }
82 const char* GetGeneralRegisterName(int code) const { 93 const char* GetGeneralRegisterName(int code) const {
83 return general_register_names_[code]; 94 return general_register_names_[code];
84 } 95 }
85 const char* GetFloatRegisterName(int code) const { 96 const char* GetFloatRegisterName(int code) const {
86 return float_register_names_[code]; 97 return float_register_names_[code];
87 } 98 }
88 const char* GetDoubleRegisterName(int code) const { 99 const char* GetDoubleRegisterName(int code) const {
89 return double_register_names_[code]; 100 return double_register_names_[code];
90 } 101 }
102 const char* GetSimd128RegisterName(int code) const {
103 return simd128_register_names_[code];
104 }
91 const int* allocatable_general_codes() const { 105 const int* allocatable_general_codes() const {
92 return allocatable_general_codes_; 106 return allocatable_general_codes_;
93 } 107 }
108 const int* allocatable_float_codes() const {
109 return allocatable_float_codes_;
110 }
94 const int* allocatable_double_codes() const { 111 const int* allocatable_double_codes() const {
95 return allocatable_double_codes_; 112 return allocatable_double_codes_;
96 } 113 }
97 const int* allocatable_float_codes() const { 114 const int* allocatable_simd128_codes() const {
98 return allocatable_float_codes_; 115 return allocatable_simd128_codes_;
99 } 116 }
100 117
101 // Aliasing calculations for floating point registers, when fp_aliasing_kind() 118 // Aliasing calculations for floating point registers, when fp_aliasing_kind()
102 // is COMBINE. Currently only implemented for kFloat32, or kFloat64 reps. 119 // is COMBINE. Currently only implemented for kFloat32, kFloat64, or kSimd128
103 // Returns the number of aliases, and if > 0, alias_base_index is set to the 120 // reps. Returns the number of aliases, and if > 0, alias_base_index is set to
104 // index of the first alias. 121 // the index of the first alias.
105 int GetAliases(MachineRepresentation rep, int index, 122 int GetAliases(MachineRepresentation rep, int index,
106 MachineRepresentation other_rep, int* alias_base_index) const; 123 MachineRepresentation other_rep, int* alias_base_index) const;
107 // Returns a value indicating whether two registers alias each other, when 124 // Returns a value indicating whether two registers alias each other, when
108 // fp_aliasing_kind() is COMBINE. Currently only implemented for kFloat32, or 125 // fp_aliasing_kind() is COMBINE. Currently implemented for kFloat32,
109 // kFloat64 reps. 126 // kFloat64, or kSimd128 reps.
110 bool AreAliases(MachineRepresentation rep, int index, 127 bool AreAliases(MachineRepresentation rep, int index,
111 MachineRepresentation other_rep, int other_index) const; 128 MachineRepresentation other_rep, int other_index) const;
112 129
113 private: 130 private:
114 const int num_general_registers_; 131 const int num_general_registers_;
115 int num_float_registers_; 132 int num_float_registers_;
116 const int num_double_registers_; 133 const int num_double_registers_;
134 int num_simd128_registers_;
117 int num_allocatable_general_registers_; 135 int num_allocatable_general_registers_;
136 int num_allocatable_float_registers_;
118 int num_allocatable_double_registers_; 137 int num_allocatable_double_registers_;
119 int num_allocatable_float_registers_; 138 int num_allocatable_simd128_registers_;
120 int32_t allocatable_general_codes_mask_; 139 int32_t allocatable_general_codes_mask_;
140 int32_t allocatable_float_codes_mask_;
121 int32_t allocatable_double_codes_mask_; 141 int32_t allocatable_double_codes_mask_;
122 int32_t allocatable_float_codes_mask_; 142 int32_t allocatable_simd128_codes_mask_;
123 const int* allocatable_general_codes_; 143 const int* allocatable_general_codes_;
144 int allocatable_float_codes_[kMaxFPRegisters];
124 const int* allocatable_double_codes_; 145 const int* allocatable_double_codes_;
125 int allocatable_float_codes_[kMaxFPRegisters]; 146 int allocatable_simd128_codes_[kMaxFPRegisters];
126 AliasingKind fp_aliasing_kind_; 147 AliasingKind fp_aliasing_kind_;
127 char const* const* general_register_names_; 148 char const* const* general_register_names_;
128 char const* const* float_register_names_; 149 char const* const* float_register_names_;
129 char const* const* double_register_names_; 150 char const* const* double_register_names_;
151 char const* const* simd128_register_names_;
130 }; 152 };
131 153
132 } // namespace internal 154 } // namespace internal
133 } // namespace v8 155 } // namespace v8
134 156
135 #endif // V8_COMPILER_REGISTER_CONFIGURATION_H_ 157 #endif // V8_COMPILER_REGISTER_CONFIGURATION_H_
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