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Issue 2092103004: [Turbofan] Add Simd128 registers to RegisterConfiguration. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Eliminate some dead code, simplify. Created 4 years, 5 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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103 V(r24) V(r25) V(r26) V(r27) V(r28) V(r30) 103 V(r24) V(r25) V(r26) V(r27) V(r28) V(r30)
104 #endif 104 #endif
105 105
106 #define DOUBLE_REGISTERS(V) \ 106 #define DOUBLE_REGISTERS(V) \
107 V(d0) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ 107 V(d0) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \
108 V(d8) V(d9) V(d10) V(d11) V(d12) V(d13) V(d14) V(d15) \ 108 V(d8) V(d9) V(d10) V(d11) V(d12) V(d13) V(d14) V(d15) \
109 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \ 109 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \
110 V(d24) V(d25) V(d26) V(d27) V(d28) V(d29) V(d30) V(d31) 110 V(d24) V(d25) V(d26) V(d27) V(d28) V(d29) V(d30) V(d31)
111 111
112 #define FLOAT_REGISTERS DOUBLE_REGISTERS 112 #define FLOAT_REGISTERS DOUBLE_REGISTERS
113 #define SIMD128_REGISTERS DOUBLE_REGISTERS
113 114
114 #define ALLOCATABLE_DOUBLE_REGISTERS(V) \ 115 #define ALLOCATABLE_DOUBLE_REGISTERS(V) \
115 V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ 116 V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \
116 V(d8) V(d9) V(d10) V(d11) V(d12) V(d15) \ 117 V(d8) V(d9) V(d10) V(d11) V(d12) V(d15) \
117 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \ 118 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \
118 V(d24) V(d25) V(d26) V(d27) V(d28) V(d29) V(d30) V(d31) 119 V(d24) V(d25) V(d26) V(d27) V(d28) V(d29) V(d30) V(d31)
119 // clang-format on 120 // clang-format on
120 121
121 // CPU Registers. 122 // CPU Registers.
122 // 123 //
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1471 1472
1472 1473
1473 class EnsureSpace BASE_EMBEDDED { 1474 class EnsureSpace BASE_EMBEDDED {
1474 public: 1475 public:
1475 explicit EnsureSpace(Assembler* assembler) { assembler->CheckBuffer(); } 1476 explicit EnsureSpace(Assembler* assembler) { assembler->CheckBuffer(); }
1476 }; 1477 };
1477 } // namespace internal 1478 } // namespace internal
1478 } // namespace v8 1479 } // namespace v8
1479 1480
1480 #endif // V8_PPC_ASSEMBLER_PPC_H_ 1481 #endif // V8_PPC_ASSEMBLER_PPC_H_
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