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Issue 2092103004: [Turbofan] Add Simd128 registers to RegisterConfiguration. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Eliminate some dead code, simplify. Created 4 years, 5 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/compiler/linkage.h" 6 #include "src/compiler/linkage.h"
7 #include "src/compiler/register-allocator.h" 7 #include "src/compiler/register-allocator.h"
8 #include "src/string-stream.h" 8 #include "src/string-stream.h"
9 9
10 namespace v8 { 10 namespace v8 {
(...skipping 1326 matching lines...) Expand 10 before | Expand all | Expand 10 after
1337 live_in_sets_(code->InstructionBlockCount(), nullptr, allocation_zone()), 1337 live_in_sets_(code->InstructionBlockCount(), nullptr, allocation_zone()),
1338 live_out_sets_(code->InstructionBlockCount(), nullptr, allocation_zone()), 1338 live_out_sets_(code->InstructionBlockCount(), nullptr, allocation_zone()),
1339 live_ranges_(code->VirtualRegisterCount() * 2, nullptr, 1339 live_ranges_(code->VirtualRegisterCount() * 2, nullptr,
1340 allocation_zone()), 1340 allocation_zone()),
1341 fixed_live_ranges_(this->config()->num_general_registers(), nullptr, 1341 fixed_live_ranges_(this->config()->num_general_registers(), nullptr,
1342 allocation_zone()), 1342 allocation_zone()),
1343 fixed_float_live_ranges_(this->config()->num_float_registers(), nullptr, 1343 fixed_float_live_ranges_(this->config()->num_float_registers(), nullptr,
1344 allocation_zone()), 1344 allocation_zone()),
1345 fixed_double_live_ranges_(this->config()->num_double_registers(), nullptr, 1345 fixed_double_live_ranges_(this->config()->num_double_registers(), nullptr,
1346 allocation_zone()), 1346 allocation_zone()),
1347 fixed_simd128_live_ranges_(this->config()->num_simd128_registers(),
1348 nullptr, allocation_zone()),
1347 spill_ranges_(code->VirtualRegisterCount(), nullptr, allocation_zone()), 1349 spill_ranges_(code->VirtualRegisterCount(), nullptr, allocation_zone()),
1348 delayed_references_(allocation_zone()), 1350 delayed_references_(allocation_zone()),
1349 assigned_registers_(nullptr), 1351 assigned_registers_(nullptr),
1350 assigned_double_registers_(nullptr), 1352 assigned_double_registers_(nullptr),
1351 virtual_register_count_(code->VirtualRegisterCount()), 1353 virtual_register_count_(code->VirtualRegisterCount()),
1352 preassigned_slot_ranges_(zone) { 1354 preassigned_slot_ranges_(zone) {
1353 assigned_registers_ = new (code_zone()) 1355 assigned_registers_ = new (code_zone())
1354 BitVector(this->config()->num_general_registers(), code_zone()); 1356 BitVector(this->config()->num_general_registers(), code_zone());
1355 assigned_double_registers_ = new (code_zone()) 1357 assigned_double_registers_ = new (code_zone())
1356 BitVector(this->config()->num_double_registers(), code_zone()); 1358 BitVector(this->config()->num_double_registers(), code_zone());
(...skipping 157 matching lines...) Expand 10 before | Expand all | Expand 10 after
1514 DCHECK(!range->IsSplinter()); 1516 DCHECK(!range->IsSplinter());
1515 SpillRange* spill_range = 1517 SpillRange* spill_range =
1516 new (allocation_zone()) SpillRange(range, allocation_zone()); 1518 new (allocation_zone()) SpillRange(range, allocation_zone());
1517 return spill_range; 1519 return spill_range;
1518 } 1520 }
1519 1521
1520 void RegisterAllocationData::MarkAllocated(MachineRepresentation rep, 1522 void RegisterAllocationData::MarkAllocated(MachineRepresentation rep,
1521 int index) { 1523 int index) {
1522 switch (rep) { 1524 switch (rep) {
1523 case MachineRepresentation::kFloat32: 1525 case MachineRepresentation::kFloat32:
1526 case MachineRepresentation::kSimd128:
1524 if (kSimpleFPAliasing) { 1527 if (kSimpleFPAliasing) {
1525 assigned_double_registers_->Add(index); 1528 assigned_double_registers_->Add(index);
1526 } else { 1529 } else {
1527 int alias_base_index = -1; 1530 int alias_base_index = -1;
1528 int aliases = config()->GetAliases( 1531 int aliases = config()->GetAliases(
1529 rep, index, MachineRepresentation::kFloat64, &alias_base_index); 1532 rep, index, MachineRepresentation::kFloat64, &alias_base_index);
1533 DCHECK(aliases > 0 || (aliases == 0 && alias_base_index == -1));
1530 while (aliases--) { 1534 while (aliases--) {
1531 int aliased_reg = alias_base_index + aliases; 1535 int aliased_reg = alias_base_index + aliases;
1532 assigned_double_registers_->Add(aliased_reg); 1536 assigned_double_registers_->Add(aliased_reg);
1533 } 1537 }
1534 } 1538 }
1535 break; 1539 break;
1536 case MachineRepresentation::kFloat64: 1540 case MachineRepresentation::kFloat64:
1537 assigned_double_registers_->Add(index); 1541 assigned_double_registers_->Add(index);
1538 break; 1542 break;
1539 default: 1543 default:
(...skipping 310 matching lines...) Expand 10 before | Expand all | Expand 10 after
1850 BitVector::Iterator iterator(live_out); 1854 BitVector::Iterator iterator(live_out);
1851 while (!iterator.Done()) { 1855 while (!iterator.Done()) {
1852 int operand_index = iterator.Current(); 1856 int operand_index = iterator.Current();
1853 TopLevelLiveRange* range = data()->GetOrCreateLiveRangeFor(operand_index); 1857 TopLevelLiveRange* range = data()->GetOrCreateLiveRangeFor(operand_index);
1854 range->AddUseInterval(start, end, allocation_zone()); 1858 range->AddUseInterval(start, end, allocation_zone());
1855 iterator.Advance(); 1859 iterator.Advance();
1856 } 1860 }
1857 } 1861 }
1858 1862
1859 int LiveRangeBuilder::FixedFPLiveRangeID(int index, MachineRepresentation rep) { 1863 int LiveRangeBuilder::FixedFPLiveRangeID(int index, MachineRepresentation rep) {
1864 int result = -index - 1;
1860 switch (rep) { 1865 switch (rep) {
1866 case MachineRepresentation::kSimd128:
1867 result -= config()->num_float_registers();
1868 // Fall through.
1861 case MachineRepresentation::kFloat32: 1869 case MachineRepresentation::kFloat32:
1862 return -index - 1 - config()->num_general_registers(); 1870 result -= config()->num_double_registers();
1871 // Fall through.
1863 case MachineRepresentation::kFloat64: 1872 case MachineRepresentation::kFloat64:
1864 return -index - 1 - config()->num_general_registers() - 1873 result -= config()->num_general_registers();
1865 config()->num_float_registers(); 1874 break;
1866 default: 1875 default:
1876 UNREACHABLE();
1867 break; 1877 break;
1868 } 1878 }
1869 UNREACHABLE(); 1879 return result;
1870 return 0;
1871 } 1880 }
1872 1881
1873 TopLevelLiveRange* LiveRangeBuilder::FixedLiveRangeFor(int index) { 1882 TopLevelLiveRange* LiveRangeBuilder::FixedLiveRangeFor(int index) {
1874 DCHECK(index < config()->num_general_registers()); 1883 DCHECK(index < config()->num_general_registers());
1875 TopLevelLiveRange* result = data()->fixed_live_ranges()[index]; 1884 TopLevelLiveRange* result = data()->fixed_live_ranges()[index];
1876 if (result == nullptr) { 1885 if (result == nullptr) {
1877 MachineRepresentation rep = InstructionSequence::DefaultRepresentation(); 1886 MachineRepresentation rep = InstructionSequence::DefaultRepresentation();
1878 result = data()->NewLiveRange(FixedLiveRangeID(index), rep); 1887 result = data()->NewLiveRange(FixedLiveRangeID(index), rep);
1879 DCHECK(result->IsFixed()); 1888 DCHECK(result->IsFixed());
1880 result->set_assigned_register(index); 1889 result->set_assigned_register(index);
1881 data()->MarkAllocated(rep, index); 1890 data()->MarkAllocated(rep, index);
1882 data()->fixed_live_ranges()[index] = result; 1891 data()->fixed_live_ranges()[index] = result;
1883 } 1892 }
1884 return result; 1893 return result;
1885 } 1894 }
1886 1895
1887 TopLevelLiveRange* LiveRangeBuilder::FixedFPLiveRangeFor( 1896 TopLevelLiveRange* LiveRangeBuilder::FixedFPLiveRangeFor(
1888 int index, MachineRepresentation rep) { 1897 int index, MachineRepresentation rep) {
1889 TopLevelLiveRange* result = nullptr; 1898 TopLevelLiveRange* result = nullptr;
1890 if (rep == MachineRepresentation::kFloat64) { 1899 switch (rep) {
1891 DCHECK(index < config()->num_double_registers()); 1900 case MachineRepresentation::kFloat32:
1892 result = data()->fixed_double_live_ranges()[index]; 1901 DCHECK(rep == MachineRepresentation::kFloat32);
1893 if (result == nullptr) { 1902 DCHECK(index < config()->num_float_registers());
1894 result = data()->NewLiveRange(FixedFPLiveRangeID(index, rep), rep); 1903 result = data()->fixed_float_live_ranges()[index];
1895 DCHECK(result->IsFixed()); 1904 if (result == nullptr) {
1896 result->set_assigned_register(index); 1905 result = data()->NewLiveRange(FixedFPLiveRangeID(index, rep), rep);
1897 data()->MarkAllocated(rep, index); 1906 DCHECK(result->IsFixed());
1898 data()->fixed_double_live_ranges()[index] = result; 1907 result->set_assigned_register(index);
1899 } 1908 data()->MarkAllocated(rep, index);
1900 } else { 1909 data()->fixed_float_live_ranges()[index] = result;
1901 DCHECK(rep == MachineRepresentation::kFloat32); 1910 }
1902 DCHECK(index < config()->num_float_registers()); 1911 break;
1903 result = data()->fixed_float_live_ranges()[index]; 1912 case MachineRepresentation::kFloat64:
1904 if (result == nullptr) { 1913 DCHECK(index < config()->num_double_registers());
1905 result = data()->NewLiveRange(FixedFPLiveRangeID(index, rep), rep); 1914 result = data()->fixed_double_live_ranges()[index];
1906 DCHECK(result->IsFixed()); 1915 if (result == nullptr) {
1907 result->set_assigned_register(index); 1916 result = data()->NewLiveRange(FixedFPLiveRangeID(index, rep), rep);
1908 data()->MarkAllocated(rep, index); 1917 DCHECK(result->IsFixed());
1909 data()->fixed_float_live_ranges()[index] = result; 1918 result->set_assigned_register(index);
1910 } 1919 data()->MarkAllocated(rep, index);
1920 data()->fixed_double_live_ranges()[index] = result;
1921 }
1922 break;
1923 case MachineRepresentation::kSimd128:
1924 DCHECK(index < config()->num_simd128_registers());
1925 result = data()->fixed_simd128_live_ranges()[index];
1926 if (result == nullptr) {
1927 result = data()->NewLiveRange(FixedFPLiveRangeID(index, rep), rep);
1928 DCHECK(result->IsFixed());
1929 result->set_assigned_register(index);
1930 data()->MarkAllocated(rep, index);
1931 data()->fixed_simd128_live_ranges()[index] = result;
1932 }
1933 break;
1934 default:
1935 UNREACHABLE();
1936 break;
1911 } 1937 }
1912 return result; 1938 return result;
1913 } 1939 }
1914 1940
1915 TopLevelLiveRange* LiveRangeBuilder::LiveRangeFor(InstructionOperand* operand) { 1941 TopLevelLiveRange* LiveRangeBuilder::LiveRangeFor(InstructionOperand* operand) {
1916 if (operand->IsUnallocated()) { 1942 if (operand->IsUnallocated()) {
1917 return data()->GetOrCreateLiveRangeFor( 1943 return data()->GetOrCreateLiveRangeFor(
1918 UnallocatedOperand::cast(operand)->virtual_register()); 1944 UnallocatedOperand::cast(operand)->virtual_register());
1919 } else if (operand->IsConstant()) { 1945 } else if (operand->IsConstant()) {
1920 return data()->GetOrCreateLiveRangeFor( 1946 return data()->GetOrCreateLiveRangeFor(
(...skipping 123 matching lines...) Expand 10 before | Expand all | Expand 10 after
2044 if (!kSimpleFPAliasing) { 2070 if (!kSimpleFPAliasing) {
2045 for (int i = 0; i < config()->num_allocatable_float_registers(); ++i) { 2071 for (int i = 0; i < config()->num_allocatable_float_registers(); ++i) {
2046 // Add a UseInterval for all FloatRegisters. See comment above for 2072 // Add a UseInterval for all FloatRegisters. See comment above for
2047 // general registers. 2073 // general registers.
2048 int code = config()->GetAllocatableFloatCode(i); 2074 int code = config()->GetAllocatableFloatCode(i);
2049 TopLevelLiveRange* range = 2075 TopLevelLiveRange* range =
2050 FixedFPLiveRangeFor(code, MachineRepresentation::kFloat32); 2076 FixedFPLiveRangeFor(code, MachineRepresentation::kFloat32);
2051 range->AddUseInterval(curr_position, curr_position.End(), 2077 range->AddUseInterval(curr_position, curr_position.End(),
2052 allocation_zone()); 2078 allocation_zone());
2053 } 2079 }
2080 for (int i = 0; i < config()->num_allocatable_simd128_registers();
2081 ++i) {
2082 int code = config()->GetAllocatableSimd128Code(i);
2083 TopLevelLiveRange* range =
2084 FixedFPLiveRangeFor(code, MachineRepresentation::kSimd128);
2085 range->AddUseInterval(curr_position, curr_position.End(),
2086 allocation_zone());
2087 }
2054 } 2088 }
2055 } 2089 }
2056 2090
2057 for (size_t i = 0; i < instr->InputCount(); i++) { 2091 for (size_t i = 0; i < instr->InputCount(); i++) {
2058 InstructionOperand* input = instr->InputAt(i); 2092 InstructionOperand* input = instr->InputAt(i);
2059 if (input->IsImmediate() || input->IsExplicit()) { 2093 if (input->IsImmediate() || input->IsExplicit()) {
2060 continue; // Ignore immediates and explicitly reserved registers. 2094 continue; // Ignore immediates and explicitly reserved registers.
2061 } 2095 }
2062 LifetimePosition use_pos; 2096 LifetimePosition use_pos;
2063 if (input->IsUnallocated() && 2097 if (input->IsUnallocated() &&
(...skipping 716 matching lines...) Expand 10 before | Expand all | Expand 10 after
2780 2814
2781 void LinearScanAllocator::InactiveToActive(LiveRange* range) { 2815 void LinearScanAllocator::InactiveToActive(LiveRange* range) {
2782 RemoveElement(&inactive_live_ranges(), range); 2816 RemoveElement(&inactive_live_ranges(), range);
2783 active_live_ranges().push_back(range); 2817 active_live_ranges().push_back(range);
2784 TRACE("Moving live range %d:%d from inactive to active\n", 2818 TRACE("Moving live range %d:%d from inactive to active\n",
2785 range->TopLevel()->vreg(), range->relative_id()); 2819 range->TopLevel()->vreg(), range->relative_id());
2786 } 2820 }
2787 2821
2788 2822
2789 bool LinearScanAllocator::TryAllocateFreeReg(LiveRange* current) { 2823 bool LinearScanAllocator::TryAllocateFreeReg(LiveRange* current) {
2824 MachineRepresentation rep = current->representation();
2790 int num_regs = num_registers(); 2825 int num_regs = num_registers();
2791 int num_codes = num_allocatable_registers(); 2826 int num_codes = num_allocatable_registers();
2792 const int* codes = allocatable_register_codes(); 2827 const int* codes = allocatable_register_codes();
2793 if (!kSimpleFPAliasing && 2828 if (!kSimpleFPAliasing) {
2794 (current->representation() == MachineRepresentation::kFloat32)) { 2829 if (rep == MachineRepresentation::kFloat32) {
2795 num_regs = data()->config()->num_float_registers(); 2830 num_regs = data()->config()->num_float_registers();
2796 num_codes = data()->config()->num_allocatable_float_registers(); 2831 num_codes = data()->config()->num_allocatable_float_registers();
2797 codes = data()->config()->allocatable_float_codes(); 2832 codes = data()->config()->allocatable_float_codes();
2833 } else if (rep == MachineRepresentation::kSimd128) {
2834 num_regs = data()->config()->num_simd128_registers();
2835 num_codes = data()->config()->num_allocatable_simd128_registers();
2836 codes = data()->config()->allocatable_simd128_codes();
2837 }
2798 } 2838 }
2839
2799 LifetimePosition free_until_pos[RegisterConfiguration::kMaxFPRegisters]; 2840 LifetimePosition free_until_pos[RegisterConfiguration::kMaxFPRegisters];
2800 for (int i = 0; i < num_regs; i++) { 2841 for (int i = 0; i < num_regs; i++) {
2801 free_until_pos[i] = LifetimePosition::MaxPosition(); 2842 free_until_pos[i] = LifetimePosition::MaxPosition();
2802 } 2843 }
2803 2844
2804 for (LiveRange* cur_active : active_live_ranges()) { 2845 for (LiveRange* cur_active : active_live_ranges()) {
2805 int cur_reg = cur_active->assigned_register(); 2846 int cur_reg = cur_active->assigned_register();
2806 if (kSimpleFPAliasing || mode() == GENERAL_REGISTERS) { 2847 if (kSimpleFPAliasing || mode() == GENERAL_REGISTERS) {
2807 free_until_pos[cur_reg] = LifetimePosition::GapFromInstructionIndex(0); 2848 free_until_pos[cur_reg] = LifetimePosition::GapFromInstructionIndex(0);
2808 TRACE("Register %s is free until pos %d (1)\n", RegisterName(cur_reg), 2849 TRACE("Register %s is free until pos %d (1)\n", RegisterName(cur_reg),
2809 LifetimePosition::GapFromInstructionIndex(0).value()); 2850 LifetimePosition::GapFromInstructionIndex(0).value());
2810 } else { 2851 } else {
2811 int alias_base_index = -1; 2852 int alias_base_index = -1;
2812 int aliases = data()->config()->GetAliases( 2853 int aliases = data()->config()->GetAliases(
2813 cur_active->representation(), cur_reg, current->representation(), 2854 cur_active->representation(), cur_reg, rep, &alias_base_index);
2814 &alias_base_index); 2855 DCHECK(aliases > 0 || (aliases == 0 && alias_base_index == -1));
2815 while (aliases--) { 2856 while (aliases--) {
2816 int aliased_reg = alias_base_index + aliases; 2857 int aliased_reg = alias_base_index + aliases;
2817 free_until_pos[aliased_reg] = 2858 free_until_pos[aliased_reg] =
2818 LifetimePosition::GapFromInstructionIndex(0); 2859 LifetimePosition::GapFromInstructionIndex(0);
2819 } 2860 }
2820 } 2861 }
2821 } 2862 }
2822 2863
2823 for (LiveRange* cur_inactive : inactive_live_ranges()) { 2864 for (LiveRange* cur_inactive : inactive_live_ranges()) {
2824 DCHECK(cur_inactive->End() > current->Start()); 2865 DCHECK(cur_inactive->End() > current->Start());
2825 LifetimePosition next_intersection = 2866 LifetimePosition next_intersection =
2826 cur_inactive->FirstIntersection(current); 2867 cur_inactive->FirstIntersection(current);
2827 if (!next_intersection.IsValid()) continue; 2868 if (!next_intersection.IsValid()) continue;
2828 int cur_reg = cur_inactive->assigned_register(); 2869 int cur_reg = cur_inactive->assigned_register();
2829 if (kSimpleFPAliasing || mode() == GENERAL_REGISTERS) { 2870 if (kSimpleFPAliasing || mode() == GENERAL_REGISTERS) {
2830 free_until_pos[cur_reg] = Min(free_until_pos[cur_reg], next_intersection); 2871 free_until_pos[cur_reg] = Min(free_until_pos[cur_reg], next_intersection);
2831 TRACE("Register %s is free until pos %d (2)\n", RegisterName(cur_reg), 2872 TRACE("Register %s is free until pos %d (2)\n", RegisterName(cur_reg),
2832 Min(free_until_pos[cur_reg], next_intersection).value()); 2873 Min(free_until_pos[cur_reg], next_intersection).value());
2833 } else { 2874 } else {
2834 int alias_base_index = -1; 2875 int alias_base_index = -1;
2835 int aliases = data()->config()->GetAliases( 2876 int aliases = data()->config()->GetAliases(
2836 cur_inactive->representation(), cur_reg, current->representation(), 2877 cur_inactive->representation(), cur_reg, rep, &alias_base_index);
2837 &alias_base_index); 2878 DCHECK(aliases > 0 || (aliases == 0 && alias_base_index == -1));
2838 while (aliases--) { 2879 while (aliases--) {
2839 int aliased_reg = alias_base_index + aliases; 2880 int aliased_reg = alias_base_index + aliases;
2840 free_until_pos[aliased_reg] = 2881 free_until_pos[aliased_reg] =
2841 Min(free_until_pos[aliased_reg], next_intersection); 2882 Min(free_until_pos[aliased_reg], next_intersection);
2842 } 2883 }
2843 } 2884 }
2844 } 2885 }
2845 2886
2846 int hint_register; 2887 int hint_register;
2847 if (current->FirstHintPosition(&hint_register) != nullptr) { 2888 if (current->FirstHintPosition(&hint_register) != nullptr) {
(...skipping 49 matching lines...) Expand 10 before | Expand all | Expand 10 after
2897 2938
2898 void LinearScanAllocator::AllocateBlockedReg(LiveRange* current) { 2939 void LinearScanAllocator::AllocateBlockedReg(LiveRange* current) {
2899 UsePosition* register_use = current->NextRegisterPosition(current->Start()); 2940 UsePosition* register_use = current->NextRegisterPosition(current->Start());
2900 if (register_use == nullptr) { 2941 if (register_use == nullptr) {
2901 // There is no use in the current live range that requires a register. 2942 // There is no use in the current live range that requires a register.
2902 // We can just spill it. 2943 // We can just spill it.
2903 Spill(current); 2944 Spill(current);
2904 return; 2945 return;
2905 } 2946 }
2906 2947
2948 MachineRepresentation rep = current->representation();
2907 int num_regs = num_registers(); 2949 int num_regs = num_registers();
2908 int num_codes = num_allocatable_registers(); 2950 int num_codes = num_allocatable_registers();
2909 const int* codes = allocatable_register_codes(); 2951 const int* codes = allocatable_register_codes();
2910 if (!kSimpleFPAliasing && 2952 if (!kSimpleFPAliasing) {
2911 (current->representation() == MachineRepresentation::kFloat32)) { 2953 if (rep == MachineRepresentation::kFloat32) {
2912 num_regs = data()->config()->num_float_registers(); 2954 num_regs = data()->config()->num_float_registers();
2913 num_codes = data()->config()->num_allocatable_float_registers(); 2955 num_codes = data()->config()->num_allocatable_float_registers();
2914 codes = data()->config()->allocatable_float_codes(); 2956 codes = data()->config()->allocatable_float_codes();
2957 } else if (rep == MachineRepresentation::kSimd128) {
2958 num_regs = data()->config()->num_simd128_registers();
2959 num_codes = data()->config()->num_allocatable_simd128_registers();
2960 codes = data()->config()->allocatable_simd128_codes();
2961 }
2915 } 2962 }
2916 2963
2917 LifetimePosition use_pos[RegisterConfiguration::kMaxFPRegisters]; 2964 LifetimePosition use_pos[RegisterConfiguration::kMaxFPRegisters];
2918 LifetimePosition block_pos[RegisterConfiguration::kMaxFPRegisters]; 2965 LifetimePosition block_pos[RegisterConfiguration::kMaxFPRegisters];
2919 for (int i = 0; i < num_regs; i++) { 2966 for (int i = 0; i < num_regs; i++) {
2920 use_pos[i] = block_pos[i] = LifetimePosition::MaxPosition(); 2967 use_pos[i] = block_pos[i] = LifetimePosition::MaxPosition();
2921 } 2968 }
2922 2969
2923 for (LiveRange* range : active_live_ranges()) { 2970 for (LiveRange* range : active_live_ranges()) {
2924 int cur_reg = range->assigned_register(); 2971 int cur_reg = range->assigned_register();
2925 bool is_fixed_or_cant_spill = 2972 bool is_fixed_or_cant_spill =
2926 range->TopLevel()->IsFixed() || !range->CanBeSpilled(current->Start()); 2973 range->TopLevel()->IsFixed() || !range->CanBeSpilled(current->Start());
2927 if (kSimpleFPAliasing || mode() == GENERAL_REGISTERS) { 2974 if (kSimpleFPAliasing || mode() == GENERAL_REGISTERS) {
2928 if (is_fixed_or_cant_spill) { 2975 if (is_fixed_or_cant_spill) {
2929 block_pos[cur_reg] = use_pos[cur_reg] = 2976 block_pos[cur_reg] = use_pos[cur_reg] =
2930 LifetimePosition::GapFromInstructionIndex(0); 2977 LifetimePosition::GapFromInstructionIndex(0);
2931 } else { 2978 } else {
2932 UsePosition* next_use = 2979 UsePosition* next_use =
2933 range->NextUsePositionRegisterIsBeneficial(current->Start()); 2980 range->NextUsePositionRegisterIsBeneficial(current->Start());
2934 if (next_use == nullptr) { 2981 if (next_use == nullptr) {
2935 use_pos[cur_reg] = range->End(); 2982 use_pos[cur_reg] = range->End();
2936 } else { 2983 } else {
2937 use_pos[cur_reg] = next_use->pos(); 2984 use_pos[cur_reg] = next_use->pos();
2938 } 2985 }
2939 } 2986 }
2940 } else { 2987 } else {
2941 int alias_base_index = -1; 2988 int alias_base_index = -1;
2942 int aliases = data()->config()->GetAliases( 2989 int aliases = data()->config()->GetAliases(
2943 range->representation(), cur_reg, current->representation(), 2990 range->representation(), cur_reg, rep, &alias_base_index);
2944 &alias_base_index); 2991 DCHECK(aliases > 0 || (aliases == 0 && alias_base_index == -1));
2945 while (aliases--) { 2992 while (aliases--) {
2946 int aliased_reg = alias_base_index + aliases; 2993 int aliased_reg = alias_base_index + aliases;
2947 if (is_fixed_or_cant_spill) { 2994 if (is_fixed_or_cant_spill) {
2948 block_pos[aliased_reg] = use_pos[aliased_reg] = 2995 block_pos[aliased_reg] = use_pos[aliased_reg] =
2949 LifetimePosition::GapFromInstructionIndex(0); 2996 LifetimePosition::GapFromInstructionIndex(0);
2950 } else { 2997 } else {
2951 UsePosition* next_use = 2998 UsePosition* next_use =
2952 range->NextUsePositionRegisterIsBeneficial(current->Start()); 2999 range->NextUsePositionRegisterIsBeneficial(current->Start());
2953 if (next_use == nullptr) { 3000 if (next_use == nullptr) {
2954 use_pos[aliased_reg] = range->End(); 3001 use_pos[aliased_reg] = range->End();
(...skipping 14 matching lines...) Expand all
2969 if (kSimpleFPAliasing || mode() == GENERAL_REGISTERS) { 3016 if (kSimpleFPAliasing || mode() == GENERAL_REGISTERS) {
2970 if (is_fixed) { 3017 if (is_fixed) {
2971 block_pos[cur_reg] = Min(block_pos[cur_reg], next_intersection); 3018 block_pos[cur_reg] = Min(block_pos[cur_reg], next_intersection);
2972 use_pos[cur_reg] = Min(block_pos[cur_reg], use_pos[cur_reg]); 3019 use_pos[cur_reg] = Min(block_pos[cur_reg], use_pos[cur_reg]);
2973 } else { 3020 } else {
2974 use_pos[cur_reg] = Min(use_pos[cur_reg], next_intersection); 3021 use_pos[cur_reg] = Min(use_pos[cur_reg], next_intersection);
2975 } 3022 }
2976 } else { 3023 } else {
2977 int alias_base_index = -1; 3024 int alias_base_index = -1;
2978 int aliases = data()->config()->GetAliases( 3025 int aliases = data()->config()->GetAliases(
2979 range->representation(), cur_reg, current->representation(), 3026 range->representation(), cur_reg, rep, &alias_base_index);
2980 &alias_base_index); 3027 DCHECK(aliases > 0 || (aliases == 0 && alias_base_index == -1));
2981 while (aliases--) { 3028 while (aliases--) {
2982 int aliased_reg = alias_base_index + aliases; 3029 int aliased_reg = alias_base_index + aliases;
2983 if (is_fixed) { 3030 if (is_fixed) {
2984 block_pos[aliased_reg] = 3031 block_pos[aliased_reg] =
2985 Min(block_pos[aliased_reg], next_intersection); 3032 Min(block_pos[aliased_reg], next_intersection);
2986 use_pos[aliased_reg] = 3033 use_pos[aliased_reg] =
2987 Min(block_pos[aliased_reg], use_pos[aliased_reg]); 3034 Min(block_pos[aliased_reg], use_pos[aliased_reg]);
2988 } else { 3035 } else {
2989 use_pos[aliased_reg] = Min(use_pos[aliased_reg], next_intersection); 3036 use_pos[aliased_reg] = Min(use_pos[aliased_reg], next_intersection);
2990 } 3037 }
(...skipping 747 matching lines...) Expand 10 before | Expand all | Expand 10 after
3738 } 3785 }
3739 } 3786 }
3740 } 3787 }
3741 } 3788 }
3742 } 3789 }
3743 3790
3744 3791
3745 } // namespace compiler 3792 } // namespace compiler
3746 } // namespace internal 3793 } // namespace internal
3747 } // namespace v8 3794 } // namespace v8
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