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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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62 V(s8) V(s9) V(s10) V(s11) V(s12) V(s13) V(s14) V(s15) \ | 62 V(s8) V(s9) V(s10) V(s11) V(s12) V(s13) V(s14) V(s15) \ |
63 V(s16) V(s17) V(s18) V(s19) V(s20) V(s21) V(s22) V(s23) \ | 63 V(s16) V(s17) V(s18) V(s19) V(s20) V(s21) V(s22) V(s23) \ |
64 V(s24) V(s25) V(s26) V(s27) V(s28) V(s29) V(s30) V(s31) | 64 V(s24) V(s25) V(s26) V(s27) V(s28) V(s29) V(s30) V(s31) |
65 | 65 |
66 #define DOUBLE_REGISTERS(V) \ | 66 #define DOUBLE_REGISTERS(V) \ |
67 V(d0) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ | 67 V(d0) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ |
68 V(d8) V(d9) V(d10) V(d11) V(d12) V(d13) V(d14) V(d15) \ | 68 V(d8) V(d9) V(d10) V(d11) V(d12) V(d13) V(d14) V(d15) \ |
69 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \ | 69 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \ |
70 V(d24) V(d25) V(d26) V(d27) V(d28) V(d29) V(d30) V(d31) | 70 V(d24) V(d25) V(d26) V(d27) V(d28) V(d29) V(d30) V(d31) |
71 | 71 |
| 72 #define SIMD128_REGISTERS(V) \ |
| 73 V(q0) V(q1) V(q2) V(q3) V(q4) V(q5) V(q6) V(q7) \ |
| 74 V(q8) V(q9) V(q10) V(q11) V(q12) V(q13) V(q14) V(q15) |
| 75 |
72 #define ALLOCATABLE_DOUBLE_REGISTERS(V) \ | 76 #define ALLOCATABLE_DOUBLE_REGISTERS(V) \ |
73 V(d0) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ | 77 V(d0) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ |
74 V(d8) V(d9) V(d10) V(d11) V(d12) V(d13) \ | 78 V(d8) V(d9) V(d10) V(d11) V(d12) V(d13) \ |
75 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \ | 79 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \ |
76 V(d24) V(d25) V(d26) V(d27) V(d28) V(d29) V(d30) V(d31) | 80 V(d24) V(d25) V(d26) V(d27) V(d28) V(d29) V(d30) V(d31) |
77 | 81 |
78 #define ALLOCATABLE_NO_VFP32_DOUBLE_REGISTERS(V) \ | 82 #define ALLOCATABLE_NO_VFP32_DOUBLE_REGISTERS(V) \ |
79 V(d0) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ | 83 V(d0) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ |
80 V(d8) V(d9) V(d10) V(d11) V(d12) V(d13) \ | 84 V(d8) V(d9) V(d10) V(d11) V(d12) V(d13) \ |
81 // clang-format on | 85 // clang-format on |
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1681 explicit EnsureSpace(Assembler* assembler) { | 1685 explicit EnsureSpace(Assembler* assembler) { |
1682 assembler->CheckBuffer(); | 1686 assembler->CheckBuffer(); |
1683 } | 1687 } |
1684 }; | 1688 }; |
1685 | 1689 |
1686 | 1690 |
1687 } // namespace internal | 1691 } // namespace internal |
1688 } // namespace v8 | 1692 } // namespace v8 |
1689 | 1693 |
1690 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1694 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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