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| 1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #include <limits.h> // For LONG_MIN, LONG_MAX. | 5 #include <limits.h> // For LONG_MIN, LONG_MAX. |
| 6 | 6 |
| 7 #if V8_TARGET_ARCH_MIPS | 7 #if V8_TARGET_ARCH_MIPS |
| 8 | 8 |
| 9 #include "src/base/bits.h" | 9 #include "src/base/bits.h" |
| 10 #include "src/base/division-by-constant.h" | 10 #include "src/base/division-by-constant.h" |
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| 1395 IsMipsArchVariant(kLoongson)); | 1395 IsMipsArchVariant(kLoongson)); |
| 1396 mfc1(scratch, fd); | 1396 mfc1(scratch, fd); |
| 1397 Usw(scratch, MemOperand(rs.rm(), rs.offset() + Register::kMantissaOffset)); | 1397 Usw(scratch, MemOperand(rs.rm(), rs.offset() + Register::kMantissaOffset)); |
| 1398 Mfhc1(scratch, fd); | 1398 Mfhc1(scratch, fd); |
| 1399 Usw(scratch, MemOperand(rs.rm(), rs.offset() + Register::kExponentOffset)); | 1399 Usw(scratch, MemOperand(rs.rm(), rs.offset() + Register::kExponentOffset)); |
| 1400 } | 1400 } |
| 1401 } | 1401 } |
| 1402 | 1402 |
| 1403 | 1403 |
| 1404 void MacroAssembler::li(Register dst, Handle<Object> value, LiFlags mode) { | 1404 void MacroAssembler::li(Register dst, Handle<Object> value, LiFlags mode) { |
| 1405 AllowDeferredHandleDereference smi_check; | 1405 li(dst, Operand(value), mode); |
| 1406 if (value->IsSmi()) { | |
| 1407 li(dst, Operand(value), mode); | |
| 1408 } else { | |
| 1409 DCHECK(value->IsHeapObject()); | |
| 1410 if (isolate()->heap()->InNewSpace(*value)) { | |
| 1411 Handle<Cell> cell = isolate()->factory()->NewCell(value); | |
| 1412 li(dst, Operand(cell)); | |
| 1413 lw(dst, FieldMemOperand(dst, Cell::kValueOffset)); | |
| 1414 } else { | |
| 1415 li(dst, Operand(value)); | |
| 1416 } | |
| 1417 } | |
| 1418 } | 1406 } |
| 1419 | 1407 |
| 1420 | 1408 |
| 1421 void MacroAssembler::li(Register rd, Operand j, LiFlags mode) { | 1409 void MacroAssembler::li(Register rd, Operand j, LiFlags mode) { |
| 1422 DCHECK(!j.is_reg()); | 1410 DCHECK(!j.is_reg()); |
| 1423 BlockTrampolinePoolScope block_trampoline_pool(this); | 1411 BlockTrampolinePoolScope block_trampoline_pool(this); |
| 1424 if (!MustUseReg(j.rmode_) && mode == OPTIMIZE_SIZE) { | 1412 if (!MustUseReg(j.rmode_) && mode == OPTIMIZE_SIZE) { |
| 1425 // Normal load of an immediate value which does not need Relocation Info. | 1413 // Normal load of an immediate value which does not need Relocation Info. |
| 1426 if (is_int16(j.imm32_)) { | 1414 if (is_int16(j.imm32_)) { |
| 1427 addiu(rd, zero_reg, j.imm32_); | 1415 addiu(rd, zero_reg, j.imm32_); |
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| 6852 if (mag.shift > 0) sra(result, result, mag.shift); | 6840 if (mag.shift > 0) sra(result, result, mag.shift); |
| 6853 srl(at, dividend, 31); | 6841 srl(at, dividend, 31); |
| 6854 Addu(result, result, Operand(at)); | 6842 Addu(result, result, Operand(at)); |
| 6855 } | 6843 } |
| 6856 | 6844 |
| 6857 | 6845 |
| 6858 } // namespace internal | 6846 } // namespace internal |
| 6859 } // namespace v8 | 6847 } // namespace v8 |
| 6860 | 6848 |
| 6861 #endif // V8_TARGET_ARCH_MIPS | 6849 #endif // V8_TARGET_ARCH_MIPS |
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