Treat ORs as ADDs for address optimization if operand has enough zero bits on the right

tests_lit/llvm2ice_tests/address-mode-opt.ll

Index: tests_lit/llvm2ice_tests/address-mode-opt.ll
diff --git a/tests_lit/llvm2ice_tests/address-mode-opt.ll b/tests_lit/llvm2ice_tests/address-mode-opt.ll
index d5c2064db4b5bb16351f6dcd0fc16e9c2bfc6bf6..d82c432786f7e3313b466d2bde52d711930ce611 100644
--- a/tests_lit/llvm2ice_tests/address-mode-opt.ll
+++ b/tests_lit/llvm2ice_tests/address-mode-opt.ll
@@ -148,3 +148,15 @@ entry:
 ; CHECK-LABEL: address_mode_opt_sub_min_int
 ; CHECK: movss xmm0,DWORD PTR [{{.*}}-0x80000000]
 }
+
+define internal float @load_1_or__2_shl_arg(float* %arg) {
+entry:
+  %arg.int = ptrtoint float* %arg to i32
+  %shl1 = shl i32 %arg.int, 2
+  %addr.int = or i32 1, %shl1

[Jim Stichnoth, 2016/06/22 20:01:14]

I would like to see two more tests:

(1) "or i32 4, %shl1"
Make sure there's no off-by-one error that incorrectly triggers the
optimization.

(2) "or i32 -1, %shl1"
Make sure there's no signed/unsigned error that incorrectly triggers the
optimization.

[manasijm, 2016/06/27 18:04:19]

Done.

+  %addr.ptr = inttoptr i32 %addr.int to float*
+  %addr.load = load float, float* %addr.ptr, align 4
+  ret float %addr.load
+; CHECK-LABEL: load_1_or__2_shl_arg
+; CHECK: movss xmm0,DWORD PTR [eax*4+0x1]

[Jim Stichnoth, 2016/06/22 20:01:14]

It would be better to not hard-code specific registers.  E.g.:

  CHECK: movss xmm{{[0-9]+}},DWORD PTR [{{e..}}*4+0x1]

[manasijm, 2016/06/27 18:04:19]

Done.

+}