Subzero, MIPS32: Cross-testing enabled for MIPS32

src/IceAssemblerMIPS32.h

 //===- subzero/src/IceAssemblerMIPS32.h - Assembler for MIPS ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 42 matching lines @@
       for (const Label *Label : LocalLabels) {
         Label->finalCheck();
       }
     }
   }
 
   void trap();
 
   void nop();
 
+  void emitRsRt(IValueT Opcode, const Operand *OpRs, const Operand *OpRt,
+                const char *InsnName);
+
   void emitRtRsImm16(IValueT Opcode, const Operand *OpRt, const Operand *OpRs,
                      uint32_t Imm, const char *InsnName);
 
   void emitFtRsImm16(IValueT Opcode, const Operand *OpFt, const Operand *OpRs,
                      uint32_t Imm, const char *InsnName);
 
   void emitRdRtSa(IValueT Opcode, const Operand *OpRd, const Operand *OpRt,
                   uint32_t Sa, const char *InsnName);
 
   void emitRdRsRt(IValueT Opcode, const Operand *OpRd, const Operand *OpRs,
@@ skipping 74 matching lines @@
   void cvt_d_s(const Operand *OpFd, const Operand *OpFs);
 
   void cvt_d_w(const Operand *OpFd, const Operand *OpFs);
 
   void cvt_s_d(const Operand *OpFd, const Operand *OpFs);
 
   void cvt_s_l(const Operand *OpFd, const Operand *OpFs);
 
   void cvt_s_w(const Operand *OpFd, const Operand *OpFs);
 
+  void div(const Operand *OpRs, const Operand *OpRt);
+
   void div_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
 
   void div_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
 
+  void lui(const Operand *OpRt, const uint16_t Imm);
+
   void lw(const Operand *OpRt, const Operand *OpBase, const uint32_t Offset);
 
   void mfc1(const Operand *OpRt, const Operand *OpFs);
 
+  void mfhi(const Operand *OpRd);
+
+  void mflo(const Operand *OpRd);
+
   void mov_d(const Operand *OpFd, const Operand *OpFs);
 
   void mov_s(const Operand *OpFd, const Operand *OpFs);
 
   void move(const Operand *OpRd, const Operand *OpRs);
 
   void movf(const Operand *OpRd, const Operand *OpRs, const Operand *OpCc);
 
   void movn(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
 
   void movn_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
 
   void movn_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
 
   void movt(const Operand *OpRd, const Operand *OpRs, const Operand *OpCc);
 
   void movz_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
 
   void movz_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
 
   void mtc1(const Operand *OpRt, const Operand *OpFs);
 
+  void mthi(const Operand *OpRs);
+
+  void mtlo(const Operand *OpRs);
+
+  void mul(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
+
   void mul_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
 
   void mul_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
 
+  void multu(const Operand *OpRs, const Operand *OpRt);
+
   void nor(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
 
   void or_(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
 
   void ori(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
 
   void ret(void);
 
   void sll(const Operand *OpRd, const Operand *OpRt, const uint32_t Sa);
 
+  void sllv(const Operand *OpRd, const Operand *OpRt, const Operand *OpRs);
+
   void slt(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
 
   void slti(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
 
   void sltiu(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
 
   void sltu(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
 
   void sqrt_d(const Operand *OpFd, const Operand *OpFs);
 
   void sqrt_s(const Operand *OpFd, const Operand *OpFs);
 
   void sra(const Operand *OpRd, const Operand *OpRt, const uint32_t Sa);
 
   void srl(const Operand *OpRd, const Operand *OpRt, const uint32_t Sa);
 
+  void srlv(const Operand *OpRd, const Operand *OpRt, const Operand *OpRs);
+
   void sub_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
 
   void sub_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
 
   void subu(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
 
   void sw(const Operand *OpRt, const Operand *OpBase, const uint32_t Offset);
 
   void teq(const Operand *OpRs, const Operand *OpRt, const uint32_t TrapCode);
 
@@ skipping 77 matching lines @@
   void emitInst(IValueT Value) {
     AssemblerBuffer::EnsureCapacity _(&Buffer);
     Buffer.emit<IValueT>(Value);
   }
 };
 
 } // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERMIPS32_H