Subzero, MIPS32: Cross-testing enabled for MIPS32

src/IceAssemblerMIPS32.cpp

 //===- subzero/src/IceAssemblerMIPS32.cpp - MIPS32 Assembler --------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 183 matching lines @@
   while (L->isLinked()) {
     IOffsetT Position = L->getLinkPosition();
     IOffsetT Dest = BoundPc - Position;
     IValueT Inst = Buffer.load<IValueT>(Position);
     Buffer.store<IValueT>(Position, encodeBranchOffset(Dest, Inst));
     L->setPosition(decodeBranchOffset(Inst));
   }
   L->bindTo(BoundPc);
 }
 
+void AssemblerMIPS32::emitRsRt(IValueT Opcode, const Operand *OpRs,
+                               const Operand *OpRt, const char *InsnName) {
+  const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName);
+  const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName);
+
+  Opcode |= Rs << 21;
+  Opcode |= Rt << 16;
+
+  emitInst(Opcode);
+}
+
 void AssemblerMIPS32::emitRtRsImm16(IValueT Opcode, const Operand *OpRt,
                                     const Operand *OpRs, const uint32_t Imm,
                                     const char *InsnName) {
   const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName);
   const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName);
 
   Opcode |= Rs << 21;
   Opcode |= Rt << 16;
   Opcode |= Imm & 0xffff;
 
@@ skipping 288 matching lines @@
 void AssemblerMIPS32::cvt_s_l(const Operand *OpFd, const Operand *OpFs) {
   static constexpr IValueT Opcode = 0x44000020;
   emitCOP1FmtFsFd(Opcode, Long, OpFd, OpFs, "cvt.s.l");
 }
 
 void AssemblerMIPS32::cvt_s_w(const Operand *OpFd, const Operand *OpFs) {
   static constexpr IValueT Opcode = 0x44000020;
   emitCOP1FmtFsFd(Opcode, Word, OpFd, OpFs, "cvt.s.w");
 }
 
+void AssemblerMIPS32::div(const Operand *OpRs, const Operand *OpRt) {
+  static constexpr IValueT Opcode = 0x0000001A;
+  emitRsRt(Opcode, OpRs, OpRt, "div");
+}
+
 void AssemblerMIPS32::div_d(const Operand *OpFd, const Operand *OpFs,
                             const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000003;
   emitCOP1FmtFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "div.d");
 }
 
 void AssemblerMIPS32::div_s(const Operand *OpFd, const Operand *OpFs,
                             const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000003;
   emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "div.s");
 }
 
+void AssemblerMIPS32::lui(const Operand *OpRt, const uint16_t Imm) {
+  IValueT Opcode = 0x3C000000;
+  const IValueT Rt = encodeGPRegister(OpRt, "Rt", "lui");
+  Opcode |= Rt << 16;
+  Opcode |= Imm;
+  emitInst(Opcode);
+}
+
 void AssemblerMIPS32::lw(const Operand *OpRt, const Operand *OpBase,
                          const uint32_t Offset) {
   switch (OpRt->getType()) {
   case IceType_i1:
   case IceType_i8: {
     static constexpr IValueT Opcode = 0x80000000;
     emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lb");
     break;
   }
   case IceType_i16: {
@@ skipping 18 matching lines @@
   }
   default: { UnimplementedError(getFlags()); }
   }
 }
 
 void AssemblerMIPS32::mfc1(const Operand *OpRt, const Operand *OpFs) {
   static constexpr IValueT Opcode = 0x44000000;
   emitCOP1MovRtFs(Opcode, OpRt, OpFs, "mfc1");
 }
 
+void AssemblerMIPS32::mfhi(const Operand *OpRd) {
+  IValueT Opcode = 0x000000010;
+  IValueT Rd = encodeGPRegister(OpRd, "Rd", "mfhi");
+  Opcode |= Rd << 11;
+  emitInst(Opcode);
+}
+
+void AssemblerMIPS32::mflo(const Operand *OpRd) {
+  IValueT Opcode = 0x000000012;
+  IValueT Rd = encodeGPRegister(OpRd, "Rd", "mflo");
+  Opcode |= Rd << 11;
+  emitInst(Opcode);
+}
+
 void AssemblerMIPS32::mov_d(const Operand *OpFd, const Operand *OpFs) {
   static constexpr IValueT Opcode = 0x44000006;
   emitCOP1FmtFsFd(Opcode, DoublePrecision, OpFd, OpFs, "mov.d");
 }
 
 void AssemblerMIPS32::mov_s(const Operand *OpFd, const Operand *OpFs) {
   static constexpr IValueT Opcode = 0x44000006;
   emitCOP1FmtFsFd(Opcode, SinglePrecision, OpFd, OpFs, "mov.s");
 }
 
@@ skipping 98 matching lines @@
                              const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000012;
   emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movz.s");
 }
 
 void AssemblerMIPS32::mtc1(const Operand *OpRt, const Operand *OpFs) {
   static constexpr IValueT Opcode = 0x44800000;
   emitCOP1MovRtFs(Opcode, OpRt, OpFs, "mtc1");
 }
 
+void AssemblerMIPS32::mthi(const Operand *OpRs) {
+  IValueT Opcode = 0x000000011;
+  IValueT Rs = encodeGPRegister(OpRs, "Rs", "mthi");
+  Opcode |= Rs << 21;
+  emitInst(Opcode);
+}
+
+void AssemblerMIPS32::mtlo(const Operand *OpRs) {
+  IValueT Opcode = 0x000000013;
+  IValueT Rs = encodeGPRegister(OpRs, "Rs", "mtlo");
+  Opcode |= Rs << 21;
+  emitInst(Opcode);
+}
+
+void AssemblerMIPS32::mul(const Operand *OpRd, const Operand *OpRs,
+                          const Operand *OpRt) {
+  static constexpr IValueT Opcode = 0x70000002;
+  emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "mul");
+}
+
 void AssemblerMIPS32::mul_d(const Operand *OpFd, const Operand *OpFs,
                             const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000002;
   emitCOP1FmtFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "mul.d");
 }
 
 void AssemblerMIPS32::mul_s(const Operand *OpFd, const Operand *OpFs,
                             const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000002;
   emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "mul.s");
 }
 
+void AssemblerMIPS32::multu(const Operand *OpRs, const Operand *OpRt) {
+  static constexpr IValueT Opcode = 0x00000019;
+  emitRsRt(Opcode, OpRs, OpRt, "multu");
+}
+
 void AssemblerMIPS32::nor(const Operand *OpRd, const Operand *OpRs,
                           const Operand *OpRt) {
   static constexpr IValueT Opcode = 0x00000027;
   emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "nor");
 }
 
 void AssemblerMIPS32::or_(const Operand *OpRd, const Operand *OpRs,
                           const Operand *OpRt) {
   static constexpr IValueT Opcode = 0x00000025;
   emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "or");
@@ skipping 10 matching lines @@
   emitInst(Opcode);
   nop(); // delay slot
 }
 
 void AssemblerMIPS32::sll(const Operand *OpRd, const Operand *OpRt,
                           const uint32_t Sa) {
   static constexpr IValueT Opcode = 0x00000000;
   emitRdRtSa(Opcode, OpRd, OpRt, Sa, "sll");
 }
 
+void AssemblerMIPS32::sllv(const Operand *OpRd, const Operand *OpRt,
+                           const Operand *OpRs) {
+  static constexpr IValueT Opcode = 0x00000004;
+  emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "sllv");
+}
+
 void AssemblerMIPS32::slt(const Operand *OpRd, const Operand *OpRs,
                           const Operand *OpRt) {
   static constexpr IValueT Opcode = 0x0000002A;
   emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "slt");
 }
 
 void AssemblerMIPS32::slti(const Operand *OpRt, const Operand *OpRs,
                            const uint32_t Imm) {
   static constexpr IValueT Opcode = 0x28000000;
   emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "slti");
@@ skipping 26 matching lines @@
   static constexpr IValueT Opcode = 0x00000003;
   emitRdRtSa(Opcode, OpRd, OpRt, Sa, "sra");
 }
 
 void AssemblerMIPS32::srl(const Operand *OpRd, const Operand *OpRt,
                           const uint32_t Sa) {
   static constexpr IValueT Opcode = 0x00000002;
   emitRdRtSa(Opcode, OpRd, OpRt, Sa, "srl");
 }
 
+void AssemblerMIPS32::srlv(const Operand *OpRd, const Operand *OpRt,
+                           const Operand *OpRs) {
+  static constexpr IValueT Opcode = 0x00000006;
+  emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "srlv");
+}
+
 void AssemblerMIPS32::sub_d(const Operand *OpFd, const Operand *OpFs,
                             const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000001;
   emitCOP1FmtFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "sub.d");
 }
 
 void AssemblerMIPS32::sub_s(const Operand *OpFd, const Operand *OpFs,
                             const Operand *OpFt) {
   static constexpr IValueT Opcode = 0x44000001;
   emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "sub.s");
@@ skipping 150 matching lines @@
     emitBr(Cond, OpRs, OpRtNone, Dest);
     return;
   }
   const IOffsetT Position = Buffer.size();
   emitBr(Cond, OpRs, OpRtNone, TargetLabel->getEncodedPosition());
   TargetLabel->linkTo(*this, Position);
 }
 
 } // end of namespace MIPS32
 } // end of namespace Ice