Use more fpu multi-load/store instructions on ARM.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 2408 matching lines @@
   if (!Address::CanHoldStoreOffset(kDWord, offset, &offset_mask)) {
     ASSERT(base != IP);
     AddImmediate(IP, base, offset & ~offset_mask, cond);
     base = IP;
     offset = offset & offset_mask;
   }
   vstrd(reg, Address(base, offset), cond);
 }
 
 
+void Assembler::LoadMultipleDFromOffset(DRegister first,
+                                        intptr_t count,
+                                        Register base,
+                                        int32_t offset) {
+  ASSERT(base != IP);
+  AddImmediate(IP, base, offset);
+  vldmd(IA, IP, first, count);
+}
+
+void Assembler::StoreMultipleDToOffset(DRegister first,
+                                       intptr_t count,
+                                       Register base,
+                                       int32_t offset) {
+  ASSERT(base != IP);
+  AddImmediate(IP, base, offset);
+  vstmd(IA, IP, first, count);
+}
+
+
 void Assembler::AddImmediate(Register rd, int32_t value, Condition cond) {
   AddImmediate(rd, rd, value, cond);
 }
 
 
 void Assembler::AddImmediate(Register rd, Register rn, int32_t value,
                              Condition cond) {
   if (value == 0) {
     if (rd != rn) {
       mov(rd, ShifterOperand(rn), cond);
@@ skipping 494 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM