MIPS: Fix 'MIPS: Followup [turbofan] Introduce new operators Float32SubPreserveNan and Float64SubPr…

src/mips/macro-assembler-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>  // For LONG_MIN, LONG_MAX.
 
 #if V8_TARGET_ARCH_MIPS
 
 #include "src/base/bits.h"
 #include "src/base/division-by-constant.h"
 #include "src/bootstrapper.h"
 #include "src/codegen.h"
 #include "src/debug/debug.h"
 #include "src/mips/macro-assembler-mips.h"
 #include "src/register-configuration.h"
 #include "src/runtime/runtime.h"
 
 namespace v8 {
 namespace internal {
 
 // Floating point constants.
 const uint32_t kDoubleSignMask = HeapNumber::kSignMask;
 const uint32_t kDoubleExponentShift = HeapNumber::kExponentShift;
 const uint32_t kDoubleNaNShift = kDoubleExponentShift - 1;
 const uint32_t kDoubleNaNMask =
-    kDoubleSignMask | HeapNumber::kExponentMask | (1 << kDoubleNaNShift);
+    HeapNumber::kExponentMask | (1 << kDoubleNaNShift);
 
 const uint32_t kSingleSignMask = kBinary32SignMask;
 const uint32_t kSingleExponentMask = kBinary32ExponentMask;
 const uint32_t kSingleExponentShift = kBinary32ExponentShift;
 const uint32_t kSingleNaNShift = kSingleExponentShift - 1;
-const uint32_t kSingleNaNMask =
-    kSingleSignMask | kSingleExponentMask | (1 << kSingleNaNShift);
+const uint32_t kSingleNaNMask = kSingleExponentMask | (1 << kSingleNaNShift);
 
 MacroAssembler::MacroAssembler(Isolate* arg_isolate, void* buffer, int size,
                                CodeObjectRequired create_code_object)
     : Assembler(arg_isolate, buffer, size),
       generating_stub_(false),
       has_frame_(false),
       has_double_zero_reg_set_(false) {
   if (create_code_object == CodeObjectRequired::kYes) {
     code_object_ =
         Handle<Object>::New(isolate()->heap()->undefined_value(), isolate());
@@ skipping 6830 matching lines @@
   if (mag.shift > 0) sra(result, result, mag.shift);
   srl(at, dividend, 31);
   Addu(result, result, Operand(at));
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS