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Side by Side Diff: src/IceTargetLoweringARM32.cpp

Issue 2080633004: Subzero: Make liveness validation errors easier to interpret. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 6 months ago
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1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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1051 Func->dump("After ARM32 codegen"); 1051 Func->dump("After ARM32 codegen");
1052 1052
1053 // Register allocation. This requires instruction renumbering and full 1053 // Register allocation. This requires instruction renumbering and full
1054 // liveness analysis. 1054 // liveness analysis.
1055 Func->renumberInstructions(); 1055 Func->renumberInstructions();
1056 if (Func->hasError()) 1056 if (Func->hasError())
1057 return; 1057 return;
1058 Func->liveness(Liveness_Intervals); 1058 Func->liveness(Liveness_Intervals);
1059 if (Func->hasError()) 1059 if (Func->hasError())
1060 return; 1060 return;
1061 // The post-codegen dump is done here, after liveness analysis and associated
1062 // cleanup, to make the dump cleaner and more useful.
1063 Func->dump("After initial ARM32 codegen");
1061 // Validate the live range computations. The expensive validation call is 1064 // Validate the live range computations. The expensive validation call is
1062 // deliberately only made when assertions are enabled. 1065 // deliberately only made when assertions are enabled.
1063 assert(Func->validateLiveness()); 1066 assert(Func->validateLiveness());
1064 // The post-codegen dump is done here, after liveness analysis and associated
1065 // cleanup, to make the dump cleaner and more useful.
1066 Func->dump("After initial ARM32 codegen");
1067 Func->getVMetadata()->init(VMK_All); 1067 Func->getVMetadata()->init(VMK_All);
1068 regAlloc(RAK_Global); 1068 regAlloc(RAK_Global);
1069 if (Func->hasError()) 1069 if (Func->hasError())
1070 return; 1070 return;
1071 1071
1072 copyRegAllocFromInfWeightVariable64On32(Func->getVariables()); 1072 copyRegAllocFromInfWeightVariable64On32(Func->getVariables());
1073 Func->dump("After linear scan regalloc"); 1073 Func->dump("After linear scan regalloc");
1074 1074
1075 if (getFlags().getEnablePhiEdgeSplit()) { 1075 if (getFlags().getEnablePhiEdgeSplit()) {
1076 Func->advancedPhiLowering(); 1076 Func->advancedPhiLowering();
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7146 // However, for compatibility with current NaCl LLVM, don't claim that. 7146 // However, for compatibility with current NaCl LLVM, don't claim that.
7147 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; 7147 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n";
7148 } 7148 }
7149 7149
7150 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM]; 7150 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
7151 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM]; 7151 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
7152 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; 7152 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
7153 7153
7154 } // end of namespace ARM32 7154 } // end of namespace ARM32
7155 } // end of namespace Ice 7155 } // end of namespace Ice
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