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Issue 20801003: MIPS: Fix debug mode webkit failures. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 7 years, 5 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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1340 | (rd.code() << kRdShift) | (1 << kSaShift) | SRLV; 1340 | (rd.code() << kRdShift) | (1 << kSaShift) | SRLV;
1341 emit(instr); 1341 emit(instr);
1342 } 1342 }
1343 1343
1344 1344
1345 //------------Memory-instructions------------- 1345 //------------Memory-instructions-------------
1346 1346
1347 // Helper for base-reg + offset, when offset is larger than int16. 1347 // Helper for base-reg + offset, when offset is larger than int16.
1348 void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) { 1348 void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) {
1349 ASSERT(!src.rm().is(at)); 1349 ASSERT(!src.rm().is(at));
1350 lui(at, src.offset_ >> kLuiShift); 1350 lui(at, (src.offset_ >> kLuiShift) & kImm16Mask);
1351 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset. 1351 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset.
1352 addu(at, at, src.rm()); // Add base register. 1352 addu(at, at, src.rm()); // Add base register.
1353 } 1353 }
1354 1354
1355 1355
1356 void Assembler::lb(Register rd, const MemOperand& rs) { 1356 void Assembler::lb(Register rd, const MemOperand& rs) {
1357 if (is_int16(rs.offset_)) { 1357 if (is_int16(rs.offset_)) {
1358 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_); 1358 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_);
1359 } else { // Offset > 16 bits, use multiple instructions to load. 1359 } else { // Offset > 16 bits, use multiple instructions to load.
1360 LoadRegPlusOffsetToAt(rs); 1360 LoadRegPlusOffsetToAt(rs);
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2295 } 2295 }
2296 2296
2297 if (patched) { 2297 if (patched) {
2298 CPU::FlushICache(pc+2, sizeof(Address)); 2298 CPU::FlushICache(pc+2, sizeof(Address));
2299 } 2299 }
2300 } 2300 }
2301 2301
2302 } } // namespace v8::internal 2302 } } // namespace v8::internal
2303 2303
2304 #endif // V8_TARGET_ARCH_MIPS 2304 #endif // V8_TARGET_ARCH_MIPS
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