OLD | NEW |
| (Empty) |
1 /* This Source Code Form is subject to the terms of the Mozilla Public | |
2 * License, v. 2.0. If a copy of the MPL was not distributed with this | |
3 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */ | |
4 | |
5 /* This implementation is by Ted Krovetz and was submitted to SUPERCOP and | |
6 * marked as public domain. It was been altered to allow for non-aligned inputs | |
7 * and to allow the block counter to be passed in specifically. */ | |
8 | |
9 #include <string.h> | |
10 | |
11 #include "chacha20.h" | |
12 | |
13 #ifndef CHACHA_RNDS | |
14 #define CHACHA_RNDS 20 /* 8 (high speed), 20 (conservative), 12 (middle) */ | |
15 #endif | |
16 | |
17 /* Architecture-neutral way to specify 16-byte vector of ints */ | |
18 typedef unsigned vec __attribute__ ((vector_size (16))); | |
19 | |
20 /* This implementation is designed for Neon, SSE and AltiVec machines. The | |
21 * following specify how to do certain vector operations efficiently on | |
22 * each architecture, using intrinsics. | |
23 * This implementation supports parallel processing of multiple blocks, | |
24 * including potentially using general-purpose registers. | |
25 */ | |
26 #if __ARM_NEON__ | |
27 #include <arm_neon.h> | |
28 #define GPR_TOO 1 | |
29 #define VBPI 2 | |
30 #define ONE (vec)vsetq_lane_u32(1,vdupq_n_u32(0),0) | |
31 #define LOAD(m) (vec)(*((vec*)(m))) | |
32 #define STORE(m,r) (*((vec*)(m))) = (r) | |
33 #define ROTV1(x) (vec)vextq_u32((uint32x4_t)x,(uint32x4_t)x,1) | |
34 #define ROTV2(x) (vec)vextq_u32((uint32x4_t)x,(uint32x4_t)x,2) | |
35 #define ROTV3(x) (vec)vextq_u32((uint32x4_t)x,(uint32x4_t)x,3) | |
36 #define ROTW16(x) (vec)vrev32q_u16((uint16x8_t)x) | |
37 #if __clang__ | |
38 #define ROTW7(x) (x << ((vec){ 7, 7, 7, 7})) ^ (x >> ((vec){25,25,25,25})) | |
39 #define ROTW8(x) (x << ((vec){ 8, 8, 8, 8})) ^ (x >> ((vec){24,24,24,24})) | |
40 #define ROTW12(x) (x << ((vec){12,12,12,12})) ^ (x >> ((vec){20,20,20,20})) | |
41 #else | |
42 #define ROTW7(x) (vec)vsriq_n_u32(vshlq_n_u32((uint32x4_t)x,7),(uint32x4_t)x,25
) | |
43 #define ROTW8(x) (vec)vsriq_n_u32(vshlq_n_u32((uint32x4_t)x,8),(uint32x4_t)x,24
) | |
44 #define ROTW12(x) (vec)vsriq_n_u32(vshlq_n_u32((uint32x4_t)x,12),(uint32x4_t)x,2
0) | |
45 #endif | |
46 #elif __SSE2__ | |
47 #include <emmintrin.h> | |
48 #define GPR_TOO 0 | |
49 #if __clang__ | |
50 #define VBPI 4 | |
51 #else | |
52 #define VBPI 3 | |
53 #endif | |
54 #define ONE (vec)_mm_set_epi32(0,0,0,1) | |
55 #define LOAD(m) (vec)_mm_loadu_si128((__m128i*)(m)) | |
56 #define STORE(m,r) _mm_storeu_si128((__m128i*)(m), (__m128i) (r)) | |
57 #define ROTV1(x) (vec)_mm_shuffle_epi32((__m128i)x,_MM_SHUFFLE(0,3,2,1)) | |
58 #define ROTV2(x) (vec)_mm_shuffle_epi32((__m128i)x,_MM_SHUFFLE(1,0,3,2)) | |
59 #define ROTV3(x) (vec)_mm_shuffle_epi32((__m128i)x,_MM_SHUFFLE(2,1,0,3)) | |
60 #define ROTW7(x) (vec)(_mm_slli_epi32((__m128i)x, 7) ^ _mm_srli_epi32((__m128i)
x,25)) | |
61 #define ROTW12(x) (vec)(_mm_slli_epi32((__m128i)x,12) ^ _mm_srli_epi32((__m128i)
x,20)) | |
62 #if __SSSE3__ | |
63 #include <tmmintrin.h> | |
64 #define ROTW8(x) (vec)_mm_shuffle_epi8((__m128i)x,_mm_set_epi8(14,13,12,15,10,9
,8,11,6,5,4,7,2,1,0,3)) | |
65 #define ROTW16(x) (vec)_mm_shuffle_epi8((__m128i)x,_mm_set_epi8(13,12,15,14,9,8,
11,10,5,4,7,6,1,0,3,2)) | |
66 #else | |
67 #define ROTW8(x) (vec)(_mm_slli_epi32((__m128i)x, 8) ^ _mm_srli_epi32((__m128i)
x,24)) | |
68 #define ROTW16(x) (vec)(_mm_slli_epi32((__m128i)x,16) ^ _mm_srli_epi32((__m128i)
x,16)) | |
69 #endif | |
70 #else | |
71 #error -- Implementation supports only machines with neon or SSE2 | |
72 #endif | |
73 | |
74 #ifndef REVV_BE | |
75 #define REVV_BE(x) (x) | |
76 #endif | |
77 | |
78 #ifndef REVW_BE | |
79 #define REVW_BE(x) (x) | |
80 #endif | |
81 | |
82 #define BPI (VBPI + GPR_TOO) /* Blocks computed per loop iteration */ | |
83 | |
84 #define DQROUND_VECTORS(a,b,c,d) \ | |
85 a += b; d ^= a; d = ROTW16(d); \ | |
86 c += d; b ^= c; b = ROTW12(b); \ | |
87 a += b; d ^= a; d = ROTW8(d); \ | |
88 c += d; b ^= c; b = ROTW7(b); \ | |
89 b = ROTV1(b); c = ROTV2(c); d = ROTV3(d); \ | |
90 a += b; d ^= a; d = ROTW16(d); \ | |
91 c += d; b ^= c; b = ROTW12(b); \ | |
92 a += b; d ^= a; d = ROTW8(d); \ | |
93 c += d; b ^= c; b = ROTW7(b); \ | |
94 b = ROTV3(b); c = ROTV2(c); d = ROTV1(d); | |
95 | |
96 #define QROUND_WORDS(a,b,c,d) \ | |
97 a = a+b; d ^= a; d = d<<16 | d>>16; \ | |
98 c = c+d; b ^= c; b = b<<12 | b>>20; \ | |
99 a = a+b; d ^= a; d = d<< 8 | d>>24; \ | |
100 c = c+d; b ^= c; b = b<< 7 | b>>25; | |
101 | |
102 #define WRITE_XOR(in, op, d, v0, v1, v2, v3) \ | |
103 STORE(op + d + 0, LOAD(in + d + 0) ^ REVV_BE(v0)); \ | |
104 STORE(op + d + 4, LOAD(in + d + 4) ^ REVV_BE(v1)); \ | |
105 STORE(op + d + 8, LOAD(in + d + 8) ^ REVV_BE(v2)); \ | |
106 STORE(op + d +12, LOAD(in + d +12) ^ REVV_BE(v3)); | |
107 | |
108 void | |
109 ChaCha20XOR(unsigned char *out, const unsigned char *in, unsigned int inlen, | |
110 const unsigned char key[32], const unsigned char nonce[12], | |
111 uint32_t counter) | |
112 { | |
113 unsigned iters, i, *op=(unsigned *)out, *ip=(unsigned *)in, *kp; | |
114 #if defined(__ARM_NEON__) | |
115 unsigned *np; | |
116 #endif | |
117 vec s0, s1, s2, s3; | |
118 #if !defined(__ARM_NEON__) && !defined(__SSE2__) | |
119 __attribute__ ((aligned (16))) unsigned key[8], nonce[4]; | |
120 #endif | |
121 __attribute__ ((aligned (16))) unsigned chacha_const[] = | |
122 {0x61707865,0x3320646E,0x79622D32,0x6B206574}; | |
123 #if defined(__ARM_NEON__) || defined(__SSE2__) | |
124 kp = (unsigned *)key; | |
125 #else | |
126 ((vec *)key)[0] = REVV_BE(((vec *)key)[0]); | |
127 ((vec *)key)[1] = REVV_BE(((vec *)key)[1]); | |
128 ((unsigned *)nonce)[0] = REVW_BE(((unsigned *)nonce)[0]); | |
129 ((unsigned *)nonce)[1] = REVW_BE(((unsigned *)nonce)[1]); | |
130 ((unsigned *)nonce)[2] = REVW_BE(((unsigned *)nonce)[2]); | |
131 ((unsigned *)nonce)[3] = REVW_BE(((unsigned *)nonce)[3]); | |
132 kp = (unsigned *)key; | |
133 np = (unsigned *)nonce; | |
134 #endif | |
135 #if defined(__ARM_NEON__) | |
136 np = (unsigned*) nonce; | |
137 #endif | |
138 s0 = LOAD(chacha_const); | |
139 s1 = LOAD(&((vec*)kp)[0]); | |
140 s2 = LOAD(&((vec*)kp)[1]); | |
141 s3 = (vec) { | |
142 counter, | |
143 ((uint32_t*)nonce)[0], | |
144 ((uint32_t*)nonce)[1], | |
145 ((uint32_t*)nonce)[2] | |
146 }; | |
147 | |
148 for (iters = 0; iters < inlen/(BPI*64); iters++) { | |
149 #if GPR_TOO | |
150 register unsigned x0, x1, x2, x3, x4, x5, x6, x7, x8, | |
151 x9, x10, x11, x12, x13, x14, x15; | |
152 #endif | |
153 #if VBPI > 2 | |
154 vec v8,v9,v10,v11; | |
155 #endif | |
156 #if VBPI > 3 | |
157 vec v12,v13,v14,v15; | |
158 #endif | |
159 | |
160 vec v0,v1,v2,v3,v4,v5,v6,v7; | |
161 v4 = v0 = s0; v5 = v1 = s1; v6 = v2 = s2; v3 = s3; | |
162 v7 = v3 + ONE; | |
163 #if VBPI > 2 | |
164 v8 = v4; v9 = v5; v10 = v6; | |
165 v11 = v7 + ONE; | |
166 #endif | |
167 #if VBPI > 3 | |
168 v12 = v8; v13 = v9; v14 = v10; | |
169 v15 = v11 + ONE; | |
170 #endif | |
171 #if GPR_TOO | |
172 x0 = chacha_const[0]; x1 = chacha_const[1]; | |
173 x2 = chacha_const[2]; x3 = chacha_const[3]; | |
174 x4 = kp[0]; x5 = kp[1]; x6 = kp[2]; x7 = kp[3]; | |
175 x8 = kp[4]; x9 = kp[5]; x10 = kp[6]; x11 = kp[7]; | |
176 x12 = counter+BPI*iters+(BPI-1); x13 = np[0]; | |
177 x14 = np[1]; x15 = np[2]; | |
178 #endif | |
179 for (i = CHACHA_RNDS/2; i; i--) { | |
180 DQROUND_VECTORS(v0,v1,v2,v3) | |
181 DQROUND_VECTORS(v4,v5,v6,v7) | |
182 #if VBPI > 2 | |
183 DQROUND_VECTORS(v8,v9,v10,v11) | |
184 #endif | |
185 #if VBPI > 3 | |
186 DQROUND_VECTORS(v12,v13,v14,v15) | |
187 #endif | |
188 #if GPR_TOO | |
189 QROUND_WORDS( x0, x4, x8,x12) | |
190 QROUND_WORDS( x1, x5, x9,x13) | |
191 QROUND_WORDS( x2, x6,x10,x14) | |
192 QROUND_WORDS( x3, x7,x11,x15) | |
193 QROUND_WORDS( x0, x5,x10,x15) | |
194 QROUND_WORDS( x1, x6,x11,x12) | |
195 QROUND_WORDS( x2, x7, x8,x13) | |
196 QROUND_WORDS( x3, x4, x9,x14) | |
197 #endif | |
198 } | |
199 | |
200 WRITE_XOR(ip, op, 0, v0+s0, v1+s1, v2+s2, v3+s3) | |
201 s3 += ONE; | |
202 WRITE_XOR(ip, op, 16, v4+s0, v5+s1, v6+s2, v7+s3) | |
203 s3 += ONE; | |
204 #if VBPI > 2 | |
205 WRITE_XOR(ip, op, 32, v8+s0, v9+s1, v10+s2, v11+s3) | |
206 s3 += ONE; | |
207 #endif | |
208 #if VBPI > 3 | |
209 WRITE_XOR(ip, op, 48, v12+s0, v13+s1, v14+s2, v15+s3) | |
210 s3 += ONE; | |
211 #endif | |
212 ip += VBPI*16; | |
213 op += VBPI*16; | |
214 #if GPR_TOO | |
215 op[0] = REVW_BE(REVW_BE(ip[0]) ^ (x0 + chacha_const[0])); | |
216 op[1] = REVW_BE(REVW_BE(ip[1]) ^ (x1 + chacha_const[1])); | |
217 op[2] = REVW_BE(REVW_BE(ip[2]) ^ (x2 + chacha_const[2])); | |
218 op[3] = REVW_BE(REVW_BE(ip[3]) ^ (x3 + chacha_const[3])); | |
219 op[4] = REVW_BE(REVW_BE(ip[4]) ^ (x4 + kp[0])); | |
220 op[5] = REVW_BE(REVW_BE(ip[5]) ^ (x5 + kp[1])); | |
221 op[6] = REVW_BE(REVW_BE(ip[6]) ^ (x6 + kp[2])); | |
222 op[7] = REVW_BE(REVW_BE(ip[7]) ^ (x7 + kp[3])); | |
223 op[8] = REVW_BE(REVW_BE(ip[8]) ^ (x8 + kp[4])); | |
224 op[9] = REVW_BE(REVW_BE(ip[9]) ^ (x9 + kp[5])); | |
225 op[10] = REVW_BE(REVW_BE(ip[10]) ^ (x10 + kp[6])); | |
226 op[11] = REVW_BE(REVW_BE(ip[11]) ^ (x11 + kp[7])); | |
227 op[12] = REVW_BE(REVW_BE(ip[12]) ^ (x12 + counter+BPI*iters+(BPI-1))); | |
228 op[13] = REVW_BE(REVW_BE(ip[13]) ^ (x13 + np[0])); | |
229 op[14] = REVW_BE(REVW_BE(ip[14]) ^ (x14 + np[1])); | |
230 op[15] = REVW_BE(REVW_BE(ip[15]) ^ (x15 + np[2])); | |
231 s3 += ONE; | |
232 ip += 16; | |
233 op += 16; | |
234 #endif | |
235 } | |
236 | |
237 for (iters = inlen%(BPI*64)/64; iters != 0; iters--) { | |
238 vec v0 = s0, v1 = s1, v2 = s2, v3 = s3; | |
239 for (i = CHACHA_RNDS/2; i; i--) { | |
240 DQROUND_VECTORS(v0,v1,v2,v3); | |
241 } | |
242 WRITE_XOR(ip, op, 0, v0+s0, v1+s1, v2+s2, v3+s3) | |
243 s3 += ONE; | |
244 ip += 16; | |
245 op += 16; | |
246 } | |
247 | |
248 inlen = inlen % 64; | |
249 if (inlen) { | |
250 __attribute__ ((aligned (16))) vec buf[4]; | |
251 vec v0,v1,v2,v3; | |
252 v0 = s0; v1 = s1; v2 = s2; v3 = s3; | |
253 for (i = CHACHA_RNDS/2; i; i--) { | |
254 DQROUND_VECTORS(v0,v1,v2,v3); | |
255 } | |
256 | |
257 if (inlen >= 16) { | |
258 STORE(op + 0, LOAD(ip + 0) ^ REVV_BE(v0 + s0)); | |
259 if (inlen >= 32) { | |
260 STORE(op + 4, LOAD(ip + 4) ^ REVV_BE(v1 + s1)); | |
261 if (inlen >= 48) { | |
262 STORE(op + 8, LOAD(ip + 8) ^ REVV_BE(v2 + s2)); | |
263 buf[3] = REVV_BE(v3 + s3); | |
264 } else { | |
265 buf[2] = REVV_BE(v2 + s2); | |
266 } | |
267 } else { | |
268 buf[1] = REVV_BE(v1 + s1); | |
269 } | |
270 } else { | |
271 buf[0] = REVV_BE(v0 + s0); | |
272 } | |
273 | |
274 for (i=inlen & ~15; i<inlen; i++) { | |
275 ((char *)op)[i] = ((char *)ip)[i] ^ ((char *)buf)[i]; | |
276 } | |
277 } | |
278 } | |
OLD | NEW |