Rename A64 port to ARM64 port

test/cctest/test-assembler-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 16 matching lines @@
 
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
 #include <cmath>
 #include <limits>
 
 #include "v8.h"
 
 #include "macro-assembler.h"
-#include "a64/simulator-a64.h"
-#include "a64/decoder-a64-inl.h"
-#include "a64/disasm-a64.h"
-#include "a64/utils-a64.h"
+#include "arm64/simulator-arm64.h"
+#include "arm64/decoder-arm64-inl.h"
+#include "arm64/disasm-arm64.h"
+#include "arm64/utils-arm64.h"
 #include "cctest.h"
-#include "test-utils-a64.h"
+#include "test-utils-arm64.h"
 
 using namespace v8::internal;
 
 // Test infrastructure.
 //
 // Tests are functions which accept no parameters and have no return values.
 // The testing code should not perform an explicit return once completed. For
 // example to test the mov immediate instruction a very simple test would be:
 //
 //   TEST(mov_x0_one) {
@@ skipping 10 matching lines @@
 //     TEARDOWN();
 //   }
 //
 // Within a START ... END block all registers but sp can be modified. sp has to
 // be explicitly saved/restored. The END() macro replaces the function return
 // so it may appear multiple times in a test if the test has multiple exit
 // points.
 //
 // Once the test has been run all integer and floating point registers as well
 // as flags are accessible through a RegisterDump instance, see
-// utils-a64.cc for more info on RegisterDump.
+// utils-arm64.cc for more info on RegisterDump.
 //
 // We provide some helper assert to handle common cases:
 //
 //   ASSERT_EQUAL_32(int32_t, int_32t)
 //   ASSERT_EQUAL_FP32(float, float)
 //   ASSERT_EQUAL_32(int32_t, W register)
 //   ASSERT_EQUAL_FP32(float, S register)
 //   ASSERT_EQUAL_64(int64_t, int_64t)
 //   ASSERT_EQUAL_FP64(double, double)
 //   ASSERT_EQUAL_64(int64_t, X register)
@@ skipping 6208 matching lines @@
   ASSERT_EQUAL_FP64(2.5f, d4);
   ASSERT_EQUAL_FP64(-1.5f, d5);
   ASSERT_EQUAL_FP64(-2.5f, d6);
   ASSERT_EQUAL_FP64(kFP64PositiveInfinity, d7);
   ASSERT_EQUAL_FP64(kFP64NegativeInfinity, d8);
   ASSERT_EQUAL_FP64(0.0f, d9);
   ASSERT_EQUAL_FP64(-0.0f, d10);
   ASSERT_EQUAL_FP64(FLT_MAX, d11);
   ASSERT_EQUAL_FP64(FLT_MIN, d12);
 
-  // Check that the NaN payload is preserved according to A64 conversion rules:
+  // Check that the NaN payload is preserved according to ARM64 conversion
+  // rules:
   //  - The sign bit is preserved.
   //  - The top bit of the mantissa is forced to 1 (making it a quiet NaN).
   //  - The remaining mantissa bits are copied until they run out.
   //  - The low-order bits that haven't already been assigned are set to 0.
   ASSERT_EQUAL_FP64(rawbits_to_double(0x7ff82468a0000000), d13);
   ASSERT_EQUAL_FP64(rawbits_to_double(0x7ff82468a0000000), d14);
 
   TEARDOWN();
 }
 
@@ skipping 4458 matching lines @@
     if (RelocInfo::IsVeneerPool(info->rmode())) {
       ASSERT(info->data() == veneer_pool_size);
       ++pool_count;
     }
   }
 
   ASSERT(pool_count == 2);
 
   TEARDOWN();
 }