Rename A64 port to ARM64 port

src/arm64/assembler-arm64-inl.h

 // Copyright 2013 the V8 project authors. All rights reserved.
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 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
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 //       with the distribution.
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 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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-#ifndef V8_A64_ASSEMBLER_A64_INL_H_
-#define V8_A64_ASSEMBLER_A64_INL_H_
+#ifndef V8_ARM64_ASSEMBLER_ARM64_INL_H_
+#define V8_ARM64_ASSEMBLER_ARM64_INL_H_
 
-#include "a64/assembler-a64.h"
+#include "arm64/assembler-arm64.h"
 #include "cpu.h"
 #include "debug.h"
 
 
 namespace v8 {
 namespace internal {
 
 
 void RelocInfo::apply(intptr_t delta) {
   UNIMPLEMENTED();
@@ skipping 524 matching lines @@
 
 Address Assembler::target_address_at(Address pc, Code* code) {
   ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
   return target_address_at(pc, constant_pool);
 }
 
 
 Address Assembler::target_address_from_return_address(Address pc) {
   // Returns the address of the call target from the return address that will
   // be returned to after a call.
-  // Call sequence on A64 is:
+  // Call sequence on ARM64 is:
   //  ldr ip0, #... @ load from literal pool
   //  blr ip0
   Address candidate = pc - 2 * kInstructionSize;
   Instruction* instr = reinterpret_cast<Instruction*>(candidate);
   USE(instr);
   ASSERT(instr->IsLdrLiteralX());
   return candidate;
 }
 
 
@@ skipping 151 matching lines @@
 void RelocInfo::set_target_cell(Cell* cell, WriteBarrierMode mode) {
   UNIMPLEMENTED();
 }
 
 
 static const int kCodeAgeSequenceSize = 5 * kInstructionSize;
 static const int kCodeAgeStubEntryOffset = 3 * kInstructionSize;
 
 
 Handle<Object> RelocInfo::code_age_stub_handle(Assembler* origin) {
-  UNREACHABLE();  // This should never be reached on A64.
+  UNREACHABLE();  // This should never be reached on ARM64.
   return Handle<Object>();
 }
 
 
 Code* RelocInfo::code_age_stub() {
   ASSERT(rmode_ == RelocInfo::CODE_AGE_SEQUENCE);
   ASSERT(!Code::IsYoungSequence(pc_));
   // Read the stub entry point from the code age sequence.
   Address stub_entry_address = pc_ + kCodeAgeStubEntryOffset;
   return Code::GetCodeFromTargetAddress(Memory::Address_at(stub_entry_address));
@@ skipping 37 matching lines @@
          IsRuntimeEntry(rmode_) ||
          IsExternalReference(rmode_));
   Assembler::set_target_address_at(pc_, host_, NULL);
 }
 
 
 bool RelocInfo::IsPatchedReturnSequence() {
   // The sequence must be:
   //   ldr ip0, [pc, #offset]
   //   blr ip0
-  // See a64/debug-a64.cc BreakLocationIterator::SetDebugBreakAtReturn().
+  // See arm64/debug-arm64.cc BreakLocationIterator::SetDebugBreakAtReturn().
   Instruction* i1 = reinterpret_cast<Instruction*>(pc_);
   Instruction* i2 = i1->following();
   return i1->IsLdrLiteralX() && (i1->Rt() == ip0.code()) &&
          i2->IsBranchAndLinkToRegister() && (i2->Rn() == ip0.code());
 }
 
 
 bool RelocInfo::IsPatchedDebugBreakSlotSequence() {
   Instruction* current_instr = reinterpret_cast<Instruction*>(pc_);
   return !current_instr->IsNop(Assembler::DEBUG_BREAK_NOP);
@@ skipping 404 matching lines @@
 }
 
 
 void Assembler::ClearRecordedAstId() {
   recorded_ast_id_ = TypeFeedbackId::None();
 }
 
 
 } }  // namespace v8::internal
 
-#endif  // V8_A64_ASSEMBLER_A64_INL_H_
+#endif  // V8_ARM64_ASSEMBLER_ARM64_INL_H_