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1 // Copyright 2013 the V8 project authors. All rights reserved. | |
2 // Redistribution and use in source and binary forms, with or without | |
3 // modification, are permitted provided that the following conditions are | |
4 // met: | |
5 // | |
6 // * Redistributions of source code must retain the above copyright | |
7 // notice, this list of conditions and the following disclaimer. | |
8 // * Redistributions in binary form must reproduce the above | |
9 // copyright notice, this list of conditions and the following | |
10 // disclaimer in the documentation and/or other materials provided | |
11 // with the distribution. | |
12 // * Neither the name of Google Inc. nor the names of its | |
13 // contributors may be used to endorse or promote products derived | |
14 // from this software without specific prior written permission. | |
15 // | |
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
27 | |
28 #ifndef V8_A64_CONSTANTS_A64_H_ | |
29 #define V8_A64_CONSTANTS_A64_H_ | |
30 | |
31 | |
32 // Assert that this is an LP64 system. | |
33 STATIC_ASSERT(sizeof(int) == sizeof(int32_t)); // NOLINT(runtime/sizeof) | |
34 STATIC_ASSERT(sizeof(long) == sizeof(int64_t)); // NOLINT(runtime/int) | |
35 STATIC_ASSERT(sizeof(void *) == sizeof(int64_t)); // NOLINT(runtime/sizeof) | |
36 STATIC_ASSERT(sizeof(1) == sizeof(int32_t)); // NOLINT(runtime/sizeof) | |
37 STATIC_ASSERT(sizeof(1L) == sizeof(int64_t)); // NOLINT(runtime/sizeof) | |
38 | |
39 | |
40 // Get the standard printf format macros for C99 stdint types. | |
41 #define __STDC_FORMAT_MACROS | |
42 #include <inttypes.h> | |
43 | |
44 | |
45 namespace v8 { | |
46 namespace internal { | |
47 | |
48 | |
49 const unsigned kInstructionSize = 4; | |
50 const unsigned kInstructionSizeLog2 = 2; | |
51 const unsigned kLiteralEntrySize = 4; | |
52 const unsigned kLiteralEntrySizeLog2 = 2; | |
53 const unsigned kMaxLoadLiteralRange = 1 * MB; | |
54 | |
55 const unsigned kNumberOfRegisters = 32; | |
56 const unsigned kNumberOfFPRegisters = 32; | |
57 // Callee saved registers are x19-x30(lr). | |
58 const int kNumberOfCalleeSavedRegisters = 11; | |
59 const int kFirstCalleeSavedRegisterIndex = 19; | |
60 // Callee saved FP registers are d8-d15. | |
61 const int kNumberOfCalleeSavedFPRegisters = 8; | |
62 const int kFirstCalleeSavedFPRegisterIndex = 8; | |
63 // Callee saved registers with no specific purpose in JS are x19-x25. | |
64 const unsigned kJSCalleeSavedRegList = 0x03f80000; | |
65 // TODO(all): k<Y>RegSize should probably be k<Y>RegSizeInBits. | |
66 const unsigned kWRegSizeInBits = 32; | |
67 const unsigned kWRegSizeInBitsLog2 = 5; | |
68 const unsigned kWRegSize = kWRegSizeInBits >> 3; | |
69 const unsigned kWRegSizeLog2 = kWRegSizeInBitsLog2 - 3; | |
70 const unsigned kXRegSizeInBits = 64; | |
71 const unsigned kXRegSizeInBitsLog2 = 6; | |
72 const unsigned kXRegSize = kXRegSizeInBits >> 3; | |
73 const unsigned kXRegSizeLog2 = kXRegSizeInBitsLog2 - 3; | |
74 const unsigned kSRegSizeInBits = 32; | |
75 const unsigned kSRegSizeInBitsLog2 = 5; | |
76 const unsigned kSRegSize = kSRegSizeInBits >> 3; | |
77 const unsigned kSRegSizeLog2 = kSRegSizeInBitsLog2 - 3; | |
78 const unsigned kDRegSizeInBits = 64; | |
79 const unsigned kDRegSizeInBitsLog2 = 6; | |
80 const unsigned kDRegSize = kDRegSizeInBits >> 3; | |
81 const unsigned kDRegSizeLog2 = kDRegSizeInBitsLog2 - 3; | |
82 const int64_t kWRegMask = 0x00000000ffffffffL; | |
83 const int64_t kXRegMask = 0xffffffffffffffffL; | |
84 const int64_t kSRegMask = 0x00000000ffffffffL; | |
85 const int64_t kDRegMask = 0xffffffffffffffffL; | |
86 // TODO(all) check if the expression below works on all compilers or if it | |
87 // triggers an overflow error. | |
88 const int64_t kDSignBit = 63; | |
89 const int64_t kDSignMask = 0x1L << kDSignBit; | |
90 const int64_t kSSignBit = 31; | |
91 const int64_t kSSignMask = 0x1L << kSSignBit; | |
92 const int64_t kXSignBit = 63; | |
93 const int64_t kXSignMask = 0x1L << kXSignBit; | |
94 const int64_t kWSignBit = 31; | |
95 const int64_t kWSignMask = 0x1L << kWSignBit; | |
96 const int64_t kDQuietNanBit = 51; | |
97 const int64_t kDQuietNanMask = 0x1L << kDQuietNanBit; | |
98 const int64_t kSQuietNanBit = 22; | |
99 const int64_t kSQuietNanMask = 0x1L << kSQuietNanBit; | |
100 const int64_t kByteMask = 0xffL; | |
101 const int64_t kHalfWordMask = 0xffffL; | |
102 const int64_t kWordMask = 0xffffffffL; | |
103 const uint64_t kXMaxUInt = 0xffffffffffffffffUL; | |
104 const uint64_t kWMaxUInt = 0xffffffffUL; | |
105 const int64_t kXMaxInt = 0x7fffffffffffffffL; | |
106 const int64_t kXMinInt = 0x8000000000000000L; | |
107 const int32_t kWMaxInt = 0x7fffffff; | |
108 const int32_t kWMinInt = 0x80000000; | |
109 const unsigned kFramePointerRegCode = 29; | |
110 const unsigned kLinkRegCode = 30; | |
111 const unsigned kZeroRegCode = 31; | |
112 const unsigned kJSSPCode = 28; | |
113 const unsigned kSPRegInternalCode = 63; | |
114 const unsigned kRegCodeMask = 0x1f; | |
115 // Standard machine types defined by AAPCS64. | |
116 const unsigned kByteSize = 8; | |
117 const unsigned kByteSizeInBytes = kByteSize >> 3; | |
118 const unsigned kHalfWordSize = 16; | |
119 const unsigned kHalfWordSizeLog2 = 4; | |
120 const unsigned kHalfWordSizeInBytes = kHalfWordSize >> 3; | |
121 const unsigned kHalfWordSizeInBytesLog2 = kHalfWordSizeLog2 - 3; | |
122 const unsigned kWordSize = 32; | |
123 const unsigned kWordSizeLog2 = 5; | |
124 const unsigned kWordSizeInBytes = kWordSize >> 3; | |
125 const unsigned kWordSizeInBytesLog2 = kWordSizeLog2 - 3; | |
126 const unsigned kDoubleWordSize = 64; | |
127 const unsigned kDoubleWordSizeInBytes = kDoubleWordSize >> 3; | |
128 const unsigned kQuadWordSize = 128; | |
129 const unsigned kQuadWordSizeInBytes = kQuadWordSize >> 3; | |
130 // AArch64 floating-point specifics. These match IEEE-754. | |
131 const unsigned kDoubleMantissaBits = 52; | |
132 const unsigned kDoubleExponentBits = 11; | |
133 const unsigned kFloatMantissaBits = 23; | |
134 const unsigned kFloatExponentBits = 8; | |
135 | |
136 #define REGISTER_CODE_LIST(R) \ | |
137 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \ | |
138 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \ | |
139 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \ | |
140 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31) | |
141 | |
142 #define INSTRUCTION_FIELDS_LIST(V_) \ | |
143 /* Register fields */ \ | |
144 V_(Rd, 4, 0, Bits) /* Destination register. */ \ | |
145 V_(Rn, 9, 5, Bits) /* First source register. */ \ | |
146 V_(Rm, 20, 16, Bits) /* Second source register. */ \ | |
147 V_(Ra, 14, 10, Bits) /* Third source register. */ \ | |
148 V_(Rt, 4, 0, Bits) /* Load dest / store source. */ \ | |
149 V_(Rt2, 14, 10, Bits) /* Load second dest / */ \ | |
150 /* store second source. */ \ | |
151 V_(PrefetchMode, 4, 0, Bits) \ | |
152 \ | |
153 /* Common bits */ \ | |
154 V_(SixtyFourBits, 31, 31, Bits) \ | |
155 V_(FlagsUpdate, 29, 29, Bits) \ | |
156 \ | |
157 /* PC relative addressing */ \ | |
158 V_(ImmPCRelHi, 23, 5, SignedBits) \ | |
159 V_(ImmPCRelLo, 30, 29, Bits) \ | |
160 \ | |
161 /* Add/subtract/logical shift register */ \ | |
162 V_(ShiftDP, 23, 22, Bits) \ | |
163 V_(ImmDPShift, 15, 10, Bits) \ | |
164 \ | |
165 /* Add/subtract immediate */ \ | |
166 V_(ImmAddSub, 21, 10, Bits) \ | |
167 V_(ShiftAddSub, 23, 22, Bits) \ | |
168 \ | |
169 /* Add/substract extend */ \ | |
170 V_(ImmExtendShift, 12, 10, Bits) \ | |
171 V_(ExtendMode, 15, 13, Bits) \ | |
172 \ | |
173 /* Move wide */ \ | |
174 V_(ImmMoveWide, 20, 5, Bits) \ | |
175 V_(ShiftMoveWide, 22, 21, Bits) \ | |
176 \ | |
177 /* Logical immediate, bitfield and extract */ \ | |
178 V_(BitN, 22, 22, Bits) \ | |
179 V_(ImmRotate, 21, 16, Bits) \ | |
180 V_(ImmSetBits, 15, 10, Bits) \ | |
181 V_(ImmR, 21, 16, Bits) \ | |
182 V_(ImmS, 15, 10, Bits) \ | |
183 \ | |
184 /* Test and branch immediate */ \ | |
185 V_(ImmTestBranch, 18, 5, SignedBits) \ | |
186 V_(ImmTestBranchBit40, 23, 19, Bits) \ | |
187 V_(ImmTestBranchBit5, 31, 31, Bits) \ | |
188 \ | |
189 /* Conditionals */ \ | |
190 V_(Condition, 15, 12, Bits) \ | |
191 V_(ConditionBranch, 3, 0, Bits) \ | |
192 V_(Nzcv, 3, 0, Bits) \ | |
193 V_(ImmCondCmp, 20, 16, Bits) \ | |
194 V_(ImmCondBranch, 23, 5, SignedBits) \ | |
195 \ | |
196 /* Floating point */ \ | |
197 V_(FPType, 23, 22, Bits) \ | |
198 V_(ImmFP, 20, 13, Bits) \ | |
199 V_(FPScale, 15, 10, Bits) \ | |
200 \ | |
201 /* Load Store */ \ | |
202 V_(ImmLS, 20, 12, SignedBits) \ | |
203 V_(ImmLSUnsigned, 21, 10, Bits) \ | |
204 V_(ImmLSPair, 21, 15, SignedBits) \ | |
205 V_(SizeLS, 31, 30, Bits) \ | |
206 V_(ImmShiftLS, 12, 12, Bits) \ | |
207 \ | |
208 /* Other immediates */ \ | |
209 V_(ImmUncondBranch, 25, 0, SignedBits) \ | |
210 V_(ImmCmpBranch, 23, 5, SignedBits) \ | |
211 V_(ImmLLiteral, 23, 5, SignedBits) \ | |
212 V_(ImmException, 20, 5, Bits) \ | |
213 V_(ImmHint, 11, 5, Bits) \ | |
214 V_(ImmBarrierDomain, 11, 10, Bits) \ | |
215 V_(ImmBarrierType, 9, 8, Bits) \ | |
216 \ | |
217 /* System (MRS, MSR) */ \ | |
218 V_(ImmSystemRegister, 19, 5, Bits) \ | |
219 V_(SysO0, 19, 19, Bits) \ | |
220 V_(SysOp1, 18, 16, Bits) \ | |
221 V_(SysOp2, 7, 5, Bits) \ | |
222 V_(CRn, 15, 12, Bits) \ | |
223 V_(CRm, 11, 8, Bits) \ | |
224 | |
225 | |
226 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \ | |
227 /* NZCV */ \ | |
228 V_(Flags, 31, 28, Bits, uint32_t) \ | |
229 V_(N, 31, 31, Bits, bool) \ | |
230 V_(Z, 30, 30, Bits, bool) \ | |
231 V_(C, 29, 29, Bits, bool) \ | |
232 V_(V, 28, 28, Bits, uint32_t) \ | |
233 M_(NZCV, Flags_mask) \ | |
234 \ | |
235 /* FPCR */ \ | |
236 V_(AHP, 26, 26, Bits, bool) \ | |
237 V_(DN, 25, 25, Bits, bool) \ | |
238 V_(FZ, 24, 24, Bits, bool) \ | |
239 V_(RMode, 23, 22, Bits, FPRounding) \ | |
240 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask) | |
241 | |
242 | |
243 // Fields offsets. | |
244 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2) \ | |
245 const int Name##_offset = LowBit; \ | |
246 const int Name##_width = HighBit - LowBit + 1; \ | |
247 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit; | |
248 #define DECLARE_INSTRUCTION_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1) \ | |
249 DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2) | |
250 #define NOTHING(A, B) | |
251 INSTRUCTION_FIELDS_LIST(DECLARE_INSTRUCTION_FIELDS_OFFSETS) | |
252 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING) | |
253 #undef NOTHING | |
254 #undef DECLARE_FIELDS_OFFSETS | |
255 #undef DECLARE_INSTRUCTION_FIELDS_OFFSETS | |
256 | |
257 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed | |
258 // from ImmPCRelLo and ImmPCRelHi. | |
259 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask; | |
260 | |
261 // Condition codes. | |
262 enum Condition { | |
263 eq = 0, | |
264 ne = 1, | |
265 hs = 2, | |
266 lo = 3, | |
267 mi = 4, | |
268 pl = 5, | |
269 vs = 6, | |
270 vc = 7, | |
271 hi = 8, | |
272 ls = 9, | |
273 ge = 10, | |
274 lt = 11, | |
275 gt = 12, | |
276 le = 13, | |
277 al = 14, | |
278 nv = 15 // Behaves as always/al. | |
279 }; | |
280 | |
281 inline Condition InvertCondition(Condition cond) { | |
282 // Conditions al and nv behave identically, as "always true". They can't be | |
283 // inverted, because there is no never condition. | |
284 ASSERT((cond != al) && (cond != nv)); | |
285 return static_cast<Condition>(cond ^ 1); | |
286 } | |
287 | |
288 // Corresponds to transposing the operands of a comparison. | |
289 inline Condition ReverseConditionForCmp(Condition cond) { | |
290 switch (cond) { | |
291 case lo: | |
292 return hi; | |
293 case hi: | |
294 return lo; | |
295 case hs: | |
296 return ls; | |
297 case ls: | |
298 return hs; | |
299 case lt: | |
300 return gt; | |
301 case gt: | |
302 return lt; | |
303 case ge: | |
304 return le; | |
305 case le: | |
306 return ge; | |
307 case eq: | |
308 return eq; | |
309 default: | |
310 // In practice this function is only used with a condition coming from | |
311 // TokenToCondition in lithium-codegen-a64.cc. Any other condition is | |
312 // invalid as it doesn't necessary make sense to reverse it (consider | |
313 // 'mi' for instance). | |
314 UNREACHABLE(); | |
315 return nv; | |
316 }; | |
317 } | |
318 | |
319 enum FlagsUpdate { | |
320 SetFlags = 1, | |
321 LeaveFlags = 0 | |
322 }; | |
323 | |
324 enum StatusFlags { | |
325 NoFlag = 0, | |
326 | |
327 // Derive the flag combinations from the system register bit descriptions. | |
328 NFlag = N_mask, | |
329 ZFlag = Z_mask, | |
330 CFlag = C_mask, | |
331 VFlag = V_mask, | |
332 NZFlag = NFlag | ZFlag, | |
333 NCFlag = NFlag | CFlag, | |
334 NVFlag = NFlag | VFlag, | |
335 ZCFlag = ZFlag | CFlag, | |
336 ZVFlag = ZFlag | VFlag, | |
337 CVFlag = CFlag | VFlag, | |
338 NZCFlag = NFlag | ZFlag | CFlag, | |
339 NZVFlag = NFlag | ZFlag | VFlag, | |
340 NCVFlag = NFlag | CFlag | VFlag, | |
341 ZCVFlag = ZFlag | CFlag | VFlag, | |
342 NZCVFlag = NFlag | ZFlag | CFlag | VFlag, | |
343 | |
344 // Floating-point comparison results. | |
345 FPEqualFlag = ZCFlag, | |
346 FPLessThanFlag = NFlag, | |
347 FPGreaterThanFlag = CFlag, | |
348 FPUnorderedFlag = CVFlag | |
349 }; | |
350 | |
351 enum Shift { | |
352 NO_SHIFT = -1, | |
353 LSL = 0x0, | |
354 LSR = 0x1, | |
355 ASR = 0x2, | |
356 ROR = 0x3 | |
357 }; | |
358 | |
359 enum Extend { | |
360 NO_EXTEND = -1, | |
361 UXTB = 0, | |
362 UXTH = 1, | |
363 UXTW = 2, | |
364 UXTX = 3, | |
365 SXTB = 4, | |
366 SXTH = 5, | |
367 SXTW = 6, | |
368 SXTX = 7 | |
369 }; | |
370 | |
371 enum SystemHint { | |
372 NOP = 0, | |
373 YIELD = 1, | |
374 WFE = 2, | |
375 WFI = 3, | |
376 SEV = 4, | |
377 SEVL = 5 | |
378 }; | |
379 | |
380 enum BarrierDomain { | |
381 OuterShareable = 0, | |
382 NonShareable = 1, | |
383 InnerShareable = 2, | |
384 FullSystem = 3 | |
385 }; | |
386 | |
387 enum BarrierType { | |
388 BarrierOther = 0, | |
389 BarrierReads = 1, | |
390 BarrierWrites = 2, | |
391 BarrierAll = 3 | |
392 }; | |
393 | |
394 // System/special register names. | |
395 // This information is not encoded as one field but as the concatenation of | |
396 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2). | |
397 enum SystemRegister { | |
398 NZCV = ((0x1 << SysO0_offset) | | |
399 (0x3 << SysOp1_offset) | | |
400 (0x4 << CRn_offset) | | |
401 (0x2 << CRm_offset) | | |
402 (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset, | |
403 FPCR = ((0x1 << SysO0_offset) | | |
404 (0x3 << SysOp1_offset) | | |
405 (0x4 << CRn_offset) | | |
406 (0x4 << CRm_offset) | | |
407 (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset | |
408 }; | |
409 | |
410 // Instruction enumerations. | |
411 // | |
412 // These are the masks that define a class of instructions, and the list of | |
413 // instructions within each class. Each enumeration has a Fixed, FMask and | |
414 // Mask value. | |
415 // | |
416 // Fixed: The fixed bits in this instruction class. | |
417 // FMask: The mask used to extract the fixed bits in the class. | |
418 // Mask: The mask used to identify the instructions within a class. | |
419 // | |
420 // The enumerations can be used like this: | |
421 // | |
422 // ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed); | |
423 // switch(instr->Mask(PCRelAddressingMask)) { | |
424 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break; | |
425 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break; | |
426 // default: printf("Unknown instruction\n"); | |
427 // } | |
428 | |
429 | |
430 // Generic fields. | |
431 enum GenericInstrField { | |
432 SixtyFourBits = 0x80000000, | |
433 ThirtyTwoBits = 0x00000000, | |
434 FP32 = 0x00000000, | |
435 FP64 = 0x00400000 | |
436 }; | |
437 | |
438 // PC relative addressing. | |
439 enum PCRelAddressingOp { | |
440 PCRelAddressingFixed = 0x10000000, | |
441 PCRelAddressingFMask = 0x1F000000, | |
442 PCRelAddressingMask = 0x9F000000, | |
443 ADR = PCRelAddressingFixed | 0x00000000, | |
444 ADRP = PCRelAddressingFixed | 0x80000000 | |
445 }; | |
446 | |
447 // Add/sub (immediate, shifted and extended.) | |
448 const int kSFOffset = 31; | |
449 enum AddSubOp { | |
450 AddSubOpMask = 0x60000000, | |
451 AddSubSetFlagsBit = 0x20000000, | |
452 ADD = 0x00000000, | |
453 ADDS = ADD | AddSubSetFlagsBit, | |
454 SUB = 0x40000000, | |
455 SUBS = SUB | AddSubSetFlagsBit | |
456 }; | |
457 | |
458 #define ADD_SUB_OP_LIST(V) \ | |
459 V(ADD), \ | |
460 V(ADDS), \ | |
461 V(SUB), \ | |
462 V(SUBS) | |
463 | |
464 enum AddSubImmediateOp { | |
465 AddSubImmediateFixed = 0x11000000, | |
466 AddSubImmediateFMask = 0x1F000000, | |
467 AddSubImmediateMask = 0xFF000000, | |
468 #define ADD_SUB_IMMEDIATE(A) \ | |
469 A##_w_imm = AddSubImmediateFixed | A, \ | |
470 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits | |
471 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE) | |
472 #undef ADD_SUB_IMMEDIATE | |
473 }; | |
474 | |
475 enum AddSubShiftedOp { | |
476 AddSubShiftedFixed = 0x0B000000, | |
477 AddSubShiftedFMask = 0x1F200000, | |
478 AddSubShiftedMask = 0xFF200000, | |
479 #define ADD_SUB_SHIFTED(A) \ | |
480 A##_w_shift = AddSubShiftedFixed | A, \ | |
481 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits | |
482 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED) | |
483 #undef ADD_SUB_SHIFTED | |
484 }; | |
485 | |
486 enum AddSubExtendedOp { | |
487 AddSubExtendedFixed = 0x0B200000, | |
488 AddSubExtendedFMask = 0x1F200000, | |
489 AddSubExtendedMask = 0xFFE00000, | |
490 #define ADD_SUB_EXTENDED(A) \ | |
491 A##_w_ext = AddSubExtendedFixed | A, \ | |
492 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits | |
493 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED) | |
494 #undef ADD_SUB_EXTENDED | |
495 }; | |
496 | |
497 // Add/sub with carry. | |
498 enum AddSubWithCarryOp { | |
499 AddSubWithCarryFixed = 0x1A000000, | |
500 AddSubWithCarryFMask = 0x1FE00000, | |
501 AddSubWithCarryMask = 0xFFE0FC00, | |
502 ADC_w = AddSubWithCarryFixed | ADD, | |
503 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits, | |
504 ADC = ADC_w, | |
505 ADCS_w = AddSubWithCarryFixed | ADDS, | |
506 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits, | |
507 SBC_w = AddSubWithCarryFixed | SUB, | |
508 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits, | |
509 SBC = SBC_w, | |
510 SBCS_w = AddSubWithCarryFixed | SUBS, | |
511 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits | |
512 }; | |
513 | |
514 | |
515 // Logical (immediate and shifted register). | |
516 enum LogicalOp { | |
517 LogicalOpMask = 0x60200000, | |
518 NOT = 0x00200000, | |
519 AND = 0x00000000, | |
520 BIC = AND | NOT, | |
521 ORR = 0x20000000, | |
522 ORN = ORR | NOT, | |
523 EOR = 0x40000000, | |
524 EON = EOR | NOT, | |
525 ANDS = 0x60000000, | |
526 BICS = ANDS | NOT | |
527 }; | |
528 | |
529 // Logical immediate. | |
530 enum LogicalImmediateOp { | |
531 LogicalImmediateFixed = 0x12000000, | |
532 LogicalImmediateFMask = 0x1F800000, | |
533 LogicalImmediateMask = 0xFF800000, | |
534 AND_w_imm = LogicalImmediateFixed | AND, | |
535 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits, | |
536 ORR_w_imm = LogicalImmediateFixed | ORR, | |
537 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits, | |
538 EOR_w_imm = LogicalImmediateFixed | EOR, | |
539 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits, | |
540 ANDS_w_imm = LogicalImmediateFixed | ANDS, | |
541 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits | |
542 }; | |
543 | |
544 // Logical shifted register. | |
545 enum LogicalShiftedOp { | |
546 LogicalShiftedFixed = 0x0A000000, | |
547 LogicalShiftedFMask = 0x1F000000, | |
548 LogicalShiftedMask = 0xFF200000, | |
549 AND_w = LogicalShiftedFixed | AND, | |
550 AND_x = LogicalShiftedFixed | AND | SixtyFourBits, | |
551 AND_shift = AND_w, | |
552 BIC_w = LogicalShiftedFixed | BIC, | |
553 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits, | |
554 BIC_shift = BIC_w, | |
555 ORR_w = LogicalShiftedFixed | ORR, | |
556 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits, | |
557 ORR_shift = ORR_w, | |
558 ORN_w = LogicalShiftedFixed | ORN, | |
559 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits, | |
560 ORN_shift = ORN_w, | |
561 EOR_w = LogicalShiftedFixed | EOR, | |
562 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits, | |
563 EOR_shift = EOR_w, | |
564 EON_w = LogicalShiftedFixed | EON, | |
565 EON_x = LogicalShiftedFixed | EON | SixtyFourBits, | |
566 EON_shift = EON_w, | |
567 ANDS_w = LogicalShiftedFixed | ANDS, | |
568 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits, | |
569 ANDS_shift = ANDS_w, | |
570 BICS_w = LogicalShiftedFixed | BICS, | |
571 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits, | |
572 BICS_shift = BICS_w | |
573 }; | |
574 | |
575 // Move wide immediate. | |
576 enum MoveWideImmediateOp { | |
577 MoveWideImmediateFixed = 0x12800000, | |
578 MoveWideImmediateFMask = 0x1F800000, | |
579 MoveWideImmediateMask = 0xFF800000, | |
580 MOVN = 0x00000000, | |
581 MOVZ = 0x40000000, | |
582 MOVK = 0x60000000, | |
583 MOVN_w = MoveWideImmediateFixed | MOVN, | |
584 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits, | |
585 MOVZ_w = MoveWideImmediateFixed | MOVZ, | |
586 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits, | |
587 MOVK_w = MoveWideImmediateFixed | MOVK, | |
588 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits | |
589 }; | |
590 | |
591 // Bitfield. | |
592 const int kBitfieldNOffset = 22; | |
593 enum BitfieldOp { | |
594 BitfieldFixed = 0x13000000, | |
595 BitfieldFMask = 0x1F800000, | |
596 BitfieldMask = 0xFF800000, | |
597 SBFM_w = BitfieldFixed | 0x00000000, | |
598 SBFM_x = BitfieldFixed | 0x80000000, | |
599 SBFM = SBFM_w, | |
600 BFM_w = BitfieldFixed | 0x20000000, | |
601 BFM_x = BitfieldFixed | 0xA0000000, | |
602 BFM = BFM_w, | |
603 UBFM_w = BitfieldFixed | 0x40000000, | |
604 UBFM_x = BitfieldFixed | 0xC0000000, | |
605 UBFM = UBFM_w | |
606 // Bitfield N field. | |
607 }; | |
608 | |
609 // Extract. | |
610 enum ExtractOp { | |
611 ExtractFixed = 0x13800000, | |
612 ExtractFMask = 0x1F800000, | |
613 ExtractMask = 0xFFA00000, | |
614 EXTR_w = ExtractFixed | 0x00000000, | |
615 EXTR_x = ExtractFixed | 0x80000000, | |
616 EXTR = EXTR_w | |
617 }; | |
618 | |
619 // Unconditional branch. | |
620 enum UnconditionalBranchOp { | |
621 UnconditionalBranchFixed = 0x14000000, | |
622 UnconditionalBranchFMask = 0x7C000000, | |
623 UnconditionalBranchMask = 0xFC000000, | |
624 B = UnconditionalBranchFixed | 0x00000000, | |
625 BL = UnconditionalBranchFixed | 0x80000000 | |
626 }; | |
627 | |
628 // Unconditional branch to register. | |
629 enum UnconditionalBranchToRegisterOp { | |
630 UnconditionalBranchToRegisterFixed = 0xD6000000, | |
631 UnconditionalBranchToRegisterFMask = 0xFE000000, | |
632 UnconditionalBranchToRegisterMask = 0xFFFFFC1F, | |
633 BR = UnconditionalBranchToRegisterFixed | 0x001F0000, | |
634 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, | |
635 RET = UnconditionalBranchToRegisterFixed | 0x005F0000 | |
636 }; | |
637 | |
638 // Compare and branch. | |
639 enum CompareBranchOp { | |
640 CompareBranchFixed = 0x34000000, | |
641 CompareBranchFMask = 0x7E000000, | |
642 CompareBranchMask = 0xFF000000, | |
643 CBZ_w = CompareBranchFixed | 0x00000000, | |
644 CBZ_x = CompareBranchFixed | 0x80000000, | |
645 CBZ = CBZ_w, | |
646 CBNZ_w = CompareBranchFixed | 0x01000000, | |
647 CBNZ_x = CompareBranchFixed | 0x81000000, | |
648 CBNZ = CBNZ_w | |
649 }; | |
650 | |
651 // Test and branch. | |
652 enum TestBranchOp { | |
653 TestBranchFixed = 0x36000000, | |
654 TestBranchFMask = 0x7E000000, | |
655 TestBranchMask = 0x7F000000, | |
656 TBZ = TestBranchFixed | 0x00000000, | |
657 TBNZ = TestBranchFixed | 0x01000000 | |
658 }; | |
659 | |
660 // Conditional branch. | |
661 enum ConditionalBranchOp { | |
662 ConditionalBranchFixed = 0x54000000, | |
663 ConditionalBranchFMask = 0xFE000000, | |
664 ConditionalBranchMask = 0xFF000010, | |
665 B_cond = ConditionalBranchFixed | 0x00000000 | |
666 }; | |
667 | |
668 // System. | |
669 // System instruction encoding is complicated because some instructions use op | |
670 // and CR fields to encode parameters. To handle this cleanly, the system | |
671 // instructions are split into more than one enum. | |
672 | |
673 enum SystemOp { | |
674 SystemFixed = 0xD5000000, | |
675 SystemFMask = 0xFFC00000 | |
676 }; | |
677 | |
678 enum SystemSysRegOp { | |
679 SystemSysRegFixed = 0xD5100000, | |
680 SystemSysRegFMask = 0xFFD00000, | |
681 SystemSysRegMask = 0xFFF00000, | |
682 MRS = SystemSysRegFixed | 0x00200000, | |
683 MSR = SystemSysRegFixed | 0x00000000 | |
684 }; | |
685 | |
686 enum SystemHintOp { | |
687 SystemHintFixed = 0xD503201F, | |
688 SystemHintFMask = 0xFFFFF01F, | |
689 SystemHintMask = 0xFFFFF01F, | |
690 HINT = SystemHintFixed | 0x00000000 | |
691 }; | |
692 | |
693 // Exception. | |
694 enum ExceptionOp { | |
695 ExceptionFixed = 0xD4000000, | |
696 ExceptionFMask = 0xFF000000, | |
697 ExceptionMask = 0xFFE0001F, | |
698 HLT = ExceptionFixed | 0x00400000, | |
699 BRK = ExceptionFixed | 0x00200000, | |
700 SVC = ExceptionFixed | 0x00000001, | |
701 HVC = ExceptionFixed | 0x00000002, | |
702 SMC = ExceptionFixed | 0x00000003, | |
703 DCPS1 = ExceptionFixed | 0x00A00001, | |
704 DCPS2 = ExceptionFixed | 0x00A00002, | |
705 DCPS3 = ExceptionFixed | 0x00A00003 | |
706 }; | |
707 // Code used to spot hlt instructions that should not be hit. | |
708 const int kHltBadCode = 0xbad; | |
709 | |
710 enum MemBarrierOp { | |
711 MemBarrierFixed = 0xD503309F, | |
712 MemBarrierFMask = 0xFFFFF09F, | |
713 MemBarrierMask = 0xFFFFF0FF, | |
714 DSB = MemBarrierFixed | 0x00000000, | |
715 DMB = MemBarrierFixed | 0x00000020, | |
716 ISB = MemBarrierFixed | 0x00000040 | |
717 }; | |
718 | |
719 // Any load or store (including pair). | |
720 enum LoadStoreAnyOp { | |
721 LoadStoreAnyFMask = 0x0a000000, | |
722 LoadStoreAnyFixed = 0x08000000 | |
723 }; | |
724 | |
725 // Any load pair or store pair. | |
726 enum LoadStorePairAnyOp { | |
727 LoadStorePairAnyFMask = 0x3a000000, | |
728 LoadStorePairAnyFixed = 0x28000000 | |
729 }; | |
730 | |
731 #define LOAD_STORE_PAIR_OP_LIST(V) \ | |
732 V(STP, w, 0x00000000), \ | |
733 V(LDP, w, 0x00400000), \ | |
734 V(LDPSW, x, 0x40400000), \ | |
735 V(STP, x, 0x80000000), \ | |
736 V(LDP, x, 0x80400000), \ | |
737 V(STP, s, 0x04000000), \ | |
738 V(LDP, s, 0x04400000), \ | |
739 V(STP, d, 0x44000000), \ | |
740 V(LDP, d, 0x44400000) | |
741 | |
742 // Load/store pair (post, pre and offset.) | |
743 enum LoadStorePairOp { | |
744 LoadStorePairMask = 0xC4400000, | |
745 LoadStorePairLBit = 1 << 22, | |
746 #define LOAD_STORE_PAIR(A, B, C) \ | |
747 A##_##B = C | |
748 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR) | |
749 #undef LOAD_STORE_PAIR | |
750 }; | |
751 | |
752 enum LoadStorePairPostIndexOp { | |
753 LoadStorePairPostIndexFixed = 0x28800000, | |
754 LoadStorePairPostIndexFMask = 0x3B800000, | |
755 LoadStorePairPostIndexMask = 0xFFC00000, | |
756 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \ | |
757 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B | |
758 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX) | |
759 #undef LOAD_STORE_PAIR_POST_INDEX | |
760 }; | |
761 | |
762 enum LoadStorePairPreIndexOp { | |
763 LoadStorePairPreIndexFixed = 0x29800000, | |
764 LoadStorePairPreIndexFMask = 0x3B800000, | |
765 LoadStorePairPreIndexMask = 0xFFC00000, | |
766 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \ | |
767 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B | |
768 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX) | |
769 #undef LOAD_STORE_PAIR_PRE_INDEX | |
770 }; | |
771 | |
772 enum LoadStorePairOffsetOp { | |
773 LoadStorePairOffsetFixed = 0x29000000, | |
774 LoadStorePairOffsetFMask = 0x3B800000, | |
775 LoadStorePairOffsetMask = 0xFFC00000, | |
776 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \ | |
777 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B | |
778 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET) | |
779 #undef LOAD_STORE_PAIR_OFFSET | |
780 }; | |
781 | |
782 enum LoadStorePairNonTemporalOp { | |
783 LoadStorePairNonTemporalFixed = 0x28000000, | |
784 LoadStorePairNonTemporalFMask = 0x3B800000, | |
785 LoadStorePairNonTemporalMask = 0xFFC00000, | |
786 STNP_w = LoadStorePairNonTemporalFixed | STP_w, | |
787 LDNP_w = LoadStorePairNonTemporalFixed | LDP_w, | |
788 STNP_x = LoadStorePairNonTemporalFixed | STP_x, | |
789 LDNP_x = LoadStorePairNonTemporalFixed | LDP_x, | |
790 STNP_s = LoadStorePairNonTemporalFixed | STP_s, | |
791 LDNP_s = LoadStorePairNonTemporalFixed | LDP_s, | |
792 STNP_d = LoadStorePairNonTemporalFixed | STP_d, | |
793 LDNP_d = LoadStorePairNonTemporalFixed | LDP_d | |
794 }; | |
795 | |
796 // Load literal. | |
797 enum LoadLiteralOp { | |
798 LoadLiteralFixed = 0x18000000, | |
799 LoadLiteralFMask = 0x3B000000, | |
800 LoadLiteralMask = 0xFF000000, | |
801 LDR_w_lit = LoadLiteralFixed | 0x00000000, | |
802 LDR_x_lit = LoadLiteralFixed | 0x40000000, | |
803 LDRSW_x_lit = LoadLiteralFixed | 0x80000000, | |
804 PRFM_lit = LoadLiteralFixed | 0xC0000000, | |
805 LDR_s_lit = LoadLiteralFixed | 0x04000000, | |
806 LDR_d_lit = LoadLiteralFixed | 0x44000000 | |
807 }; | |
808 | |
809 #define LOAD_STORE_OP_LIST(V) \ | |
810 V(ST, RB, w, 0x00000000), \ | |
811 V(ST, RH, w, 0x40000000), \ | |
812 V(ST, R, w, 0x80000000), \ | |
813 V(ST, R, x, 0xC0000000), \ | |
814 V(LD, RB, w, 0x00400000), \ | |
815 V(LD, RH, w, 0x40400000), \ | |
816 V(LD, R, w, 0x80400000), \ | |
817 V(LD, R, x, 0xC0400000), \ | |
818 V(LD, RSB, x, 0x00800000), \ | |
819 V(LD, RSH, x, 0x40800000), \ | |
820 V(LD, RSW, x, 0x80800000), \ | |
821 V(LD, RSB, w, 0x00C00000), \ | |
822 V(LD, RSH, w, 0x40C00000), \ | |
823 V(ST, R, s, 0x84000000), \ | |
824 V(ST, R, d, 0xC4000000), \ | |
825 V(LD, R, s, 0x84400000), \ | |
826 V(LD, R, d, 0xC4400000) | |
827 | |
828 | |
829 // Load/store unscaled offset. | |
830 enum LoadStoreUnscaledOffsetOp { | |
831 LoadStoreUnscaledOffsetFixed = 0x38000000, | |
832 LoadStoreUnscaledOffsetFMask = 0x3B200C00, | |
833 LoadStoreUnscaledOffsetMask = 0xFFE00C00, | |
834 #define LOAD_STORE_UNSCALED(A, B, C, D) \ | |
835 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D | |
836 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED) | |
837 #undef LOAD_STORE_UNSCALED | |
838 }; | |
839 | |
840 // Load/store (post, pre, offset and unsigned.) | |
841 enum LoadStoreOp { | |
842 LoadStoreOpMask = 0xC4C00000, | |
843 #define LOAD_STORE(A, B, C, D) \ | |
844 A##B##_##C = D | |
845 LOAD_STORE_OP_LIST(LOAD_STORE), | |
846 #undef LOAD_STORE | |
847 PRFM = 0xC0800000 | |
848 }; | |
849 | |
850 // Load/store post index. | |
851 enum LoadStorePostIndex { | |
852 LoadStorePostIndexFixed = 0x38000400, | |
853 LoadStorePostIndexFMask = 0x3B200C00, | |
854 LoadStorePostIndexMask = 0xFFE00C00, | |
855 #define LOAD_STORE_POST_INDEX(A, B, C, D) \ | |
856 A##B##_##C##_post = LoadStorePostIndexFixed | D | |
857 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX) | |
858 #undef LOAD_STORE_POST_INDEX | |
859 }; | |
860 | |
861 // Load/store pre index. | |
862 enum LoadStorePreIndex { | |
863 LoadStorePreIndexFixed = 0x38000C00, | |
864 LoadStorePreIndexFMask = 0x3B200C00, | |
865 LoadStorePreIndexMask = 0xFFE00C00, | |
866 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \ | |
867 A##B##_##C##_pre = LoadStorePreIndexFixed | D | |
868 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX) | |
869 #undef LOAD_STORE_PRE_INDEX | |
870 }; | |
871 | |
872 // Load/store unsigned offset. | |
873 enum LoadStoreUnsignedOffset { | |
874 LoadStoreUnsignedOffsetFixed = 0x39000000, | |
875 LoadStoreUnsignedOffsetFMask = 0x3B000000, | |
876 LoadStoreUnsignedOffsetMask = 0xFFC00000, | |
877 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM, | |
878 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \ | |
879 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D | |
880 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET) | |
881 #undef LOAD_STORE_UNSIGNED_OFFSET | |
882 }; | |
883 | |
884 // Load/store register offset. | |
885 enum LoadStoreRegisterOffset { | |
886 LoadStoreRegisterOffsetFixed = 0x38200800, | |
887 LoadStoreRegisterOffsetFMask = 0x3B200C00, | |
888 LoadStoreRegisterOffsetMask = 0xFFE00C00, | |
889 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM, | |
890 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \ | |
891 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D | |
892 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET) | |
893 #undef LOAD_STORE_REGISTER_OFFSET | |
894 }; | |
895 | |
896 // Conditional compare. | |
897 enum ConditionalCompareOp { | |
898 ConditionalCompareMask = 0x60000000, | |
899 CCMN = 0x20000000, | |
900 CCMP = 0x60000000 | |
901 }; | |
902 | |
903 // Conditional compare register. | |
904 enum ConditionalCompareRegisterOp { | |
905 ConditionalCompareRegisterFixed = 0x1A400000, | |
906 ConditionalCompareRegisterFMask = 0x1FE00800, | |
907 ConditionalCompareRegisterMask = 0xFFE00C10, | |
908 CCMN_w = ConditionalCompareRegisterFixed | CCMN, | |
909 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN, | |
910 CCMP_w = ConditionalCompareRegisterFixed | CCMP, | |
911 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP | |
912 }; | |
913 | |
914 // Conditional compare immediate. | |
915 enum ConditionalCompareImmediateOp { | |
916 ConditionalCompareImmediateFixed = 0x1A400800, | |
917 ConditionalCompareImmediateFMask = 0x1FE00800, | |
918 ConditionalCompareImmediateMask = 0xFFE00C10, | |
919 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN, | |
920 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN, | |
921 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP, | |
922 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP | |
923 }; | |
924 | |
925 // Conditional select. | |
926 enum ConditionalSelectOp { | |
927 ConditionalSelectFixed = 0x1A800000, | |
928 ConditionalSelectFMask = 0x1FE00000, | |
929 ConditionalSelectMask = 0xFFE00C00, | |
930 CSEL_w = ConditionalSelectFixed | 0x00000000, | |
931 CSEL_x = ConditionalSelectFixed | 0x80000000, | |
932 CSEL = CSEL_w, | |
933 CSINC_w = ConditionalSelectFixed | 0x00000400, | |
934 CSINC_x = ConditionalSelectFixed | 0x80000400, | |
935 CSINC = CSINC_w, | |
936 CSINV_w = ConditionalSelectFixed | 0x40000000, | |
937 CSINV_x = ConditionalSelectFixed | 0xC0000000, | |
938 CSINV = CSINV_w, | |
939 CSNEG_w = ConditionalSelectFixed | 0x40000400, | |
940 CSNEG_x = ConditionalSelectFixed | 0xC0000400, | |
941 CSNEG = CSNEG_w | |
942 }; | |
943 | |
944 // Data processing 1 source. | |
945 enum DataProcessing1SourceOp { | |
946 DataProcessing1SourceFixed = 0x5AC00000, | |
947 DataProcessing1SourceFMask = 0x5FE00000, | |
948 DataProcessing1SourceMask = 0xFFFFFC00, | |
949 RBIT = DataProcessing1SourceFixed | 0x00000000, | |
950 RBIT_w = RBIT, | |
951 RBIT_x = RBIT | SixtyFourBits, | |
952 REV16 = DataProcessing1SourceFixed | 0x00000400, | |
953 REV16_w = REV16, | |
954 REV16_x = REV16 | SixtyFourBits, | |
955 REV = DataProcessing1SourceFixed | 0x00000800, | |
956 REV_w = REV, | |
957 REV32_x = REV | SixtyFourBits, | |
958 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00, | |
959 CLZ = DataProcessing1SourceFixed | 0x00001000, | |
960 CLZ_w = CLZ, | |
961 CLZ_x = CLZ | SixtyFourBits, | |
962 CLS = DataProcessing1SourceFixed | 0x00001400, | |
963 CLS_w = CLS, | |
964 CLS_x = CLS | SixtyFourBits | |
965 }; | |
966 | |
967 // Data processing 2 source. | |
968 enum DataProcessing2SourceOp { | |
969 DataProcessing2SourceFixed = 0x1AC00000, | |
970 DataProcessing2SourceFMask = 0x5FE00000, | |
971 DataProcessing2SourceMask = 0xFFE0FC00, | |
972 UDIV_w = DataProcessing2SourceFixed | 0x00000800, | |
973 UDIV_x = DataProcessing2SourceFixed | 0x80000800, | |
974 UDIV = UDIV_w, | |
975 SDIV_w = DataProcessing2SourceFixed | 0x00000C00, | |
976 SDIV_x = DataProcessing2SourceFixed | 0x80000C00, | |
977 SDIV = SDIV_w, | |
978 LSLV_w = DataProcessing2SourceFixed | 0x00002000, | |
979 LSLV_x = DataProcessing2SourceFixed | 0x80002000, | |
980 LSLV = LSLV_w, | |
981 LSRV_w = DataProcessing2SourceFixed | 0x00002400, | |
982 LSRV_x = DataProcessing2SourceFixed | 0x80002400, | |
983 LSRV = LSRV_w, | |
984 ASRV_w = DataProcessing2SourceFixed | 0x00002800, | |
985 ASRV_x = DataProcessing2SourceFixed | 0x80002800, | |
986 ASRV = ASRV_w, | |
987 RORV_w = DataProcessing2SourceFixed | 0x00002C00, | |
988 RORV_x = DataProcessing2SourceFixed | 0x80002C00, | |
989 RORV = RORV_w, | |
990 CRC32B = DataProcessing2SourceFixed | 0x00004000, | |
991 CRC32H = DataProcessing2SourceFixed | 0x00004400, | |
992 CRC32W = DataProcessing2SourceFixed | 0x00004800, | |
993 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00, | |
994 CRC32CB = DataProcessing2SourceFixed | 0x00005000, | |
995 CRC32CH = DataProcessing2SourceFixed | 0x00005400, | |
996 CRC32CW = DataProcessing2SourceFixed | 0x00005800, | |
997 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00 | |
998 }; | |
999 | |
1000 // Data processing 3 source. | |
1001 enum DataProcessing3SourceOp { | |
1002 DataProcessing3SourceFixed = 0x1B000000, | |
1003 DataProcessing3SourceFMask = 0x1F000000, | |
1004 DataProcessing3SourceMask = 0xFFE08000, | |
1005 MADD_w = DataProcessing3SourceFixed | 0x00000000, | |
1006 MADD_x = DataProcessing3SourceFixed | 0x80000000, | |
1007 MADD = MADD_w, | |
1008 MSUB_w = DataProcessing3SourceFixed | 0x00008000, | |
1009 MSUB_x = DataProcessing3SourceFixed | 0x80008000, | |
1010 MSUB = MSUB_w, | |
1011 SMADDL_x = DataProcessing3SourceFixed | 0x80200000, | |
1012 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000, | |
1013 SMULH_x = DataProcessing3SourceFixed | 0x80400000, | |
1014 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000, | |
1015 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000, | |
1016 UMULH_x = DataProcessing3SourceFixed | 0x80C00000 | |
1017 }; | |
1018 | |
1019 // Floating point compare. | |
1020 enum FPCompareOp { | |
1021 FPCompareFixed = 0x1E202000, | |
1022 FPCompareFMask = 0x5F203C00, | |
1023 FPCompareMask = 0xFFE0FC1F, | |
1024 FCMP_s = FPCompareFixed | 0x00000000, | |
1025 FCMP_d = FPCompareFixed | FP64 | 0x00000000, | |
1026 FCMP = FCMP_s, | |
1027 FCMP_s_zero = FPCompareFixed | 0x00000008, | |
1028 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008, | |
1029 FCMP_zero = FCMP_s_zero, | |
1030 FCMPE_s = FPCompareFixed | 0x00000010, | |
1031 FCMPE_d = FPCompareFixed | FP64 | 0x00000010, | |
1032 FCMPE_s_zero = FPCompareFixed | 0x00000018, | |
1033 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018 | |
1034 }; | |
1035 | |
1036 // Floating point conditional compare. | |
1037 enum FPConditionalCompareOp { | |
1038 FPConditionalCompareFixed = 0x1E200400, | |
1039 FPConditionalCompareFMask = 0x5F200C00, | |
1040 FPConditionalCompareMask = 0xFFE00C10, | |
1041 FCCMP_s = FPConditionalCompareFixed | 0x00000000, | |
1042 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000, | |
1043 FCCMP = FCCMP_s, | |
1044 FCCMPE_s = FPConditionalCompareFixed | 0x00000010, | |
1045 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010, | |
1046 FCCMPE = FCCMPE_s | |
1047 }; | |
1048 | |
1049 // Floating point conditional select. | |
1050 enum FPConditionalSelectOp { | |
1051 FPConditionalSelectFixed = 0x1E200C00, | |
1052 FPConditionalSelectFMask = 0x5F200C00, | |
1053 FPConditionalSelectMask = 0xFFE00C00, | |
1054 FCSEL_s = FPConditionalSelectFixed | 0x00000000, | |
1055 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000, | |
1056 FCSEL = FCSEL_s | |
1057 }; | |
1058 | |
1059 // Floating point immediate. | |
1060 enum FPImmediateOp { | |
1061 FPImmediateFixed = 0x1E201000, | |
1062 FPImmediateFMask = 0x5F201C00, | |
1063 FPImmediateMask = 0xFFE01C00, | |
1064 FMOV_s_imm = FPImmediateFixed | 0x00000000, | |
1065 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000 | |
1066 }; | |
1067 | |
1068 // Floating point data processing 1 source. | |
1069 enum FPDataProcessing1SourceOp { | |
1070 FPDataProcessing1SourceFixed = 0x1E204000, | |
1071 FPDataProcessing1SourceFMask = 0x5F207C00, | |
1072 FPDataProcessing1SourceMask = 0xFFFFFC00, | |
1073 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000, | |
1074 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000, | |
1075 FMOV = FMOV_s, | |
1076 FABS_s = FPDataProcessing1SourceFixed | 0x00008000, | |
1077 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000, | |
1078 FABS = FABS_s, | |
1079 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000, | |
1080 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000, | |
1081 FNEG = FNEG_s, | |
1082 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000, | |
1083 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000, | |
1084 FSQRT = FSQRT_s, | |
1085 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000, | |
1086 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000, | |
1087 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000, | |
1088 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000, | |
1089 FRINTN = FRINTN_s, | |
1090 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000, | |
1091 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000, | |
1092 FRINTP = FRINTP_s, | |
1093 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000, | |
1094 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000, | |
1095 FRINTM = FRINTM_s, | |
1096 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000, | |
1097 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000, | |
1098 FRINTZ = FRINTZ_s, | |
1099 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000, | |
1100 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000, | |
1101 FRINTA = FRINTA_s, | |
1102 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000, | |
1103 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000, | |
1104 FRINTX = FRINTX_s, | |
1105 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000, | |
1106 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000, | |
1107 FRINTI = FRINTI_s | |
1108 }; | |
1109 | |
1110 // Floating point data processing 2 source. | |
1111 enum FPDataProcessing2SourceOp { | |
1112 FPDataProcessing2SourceFixed = 0x1E200800, | |
1113 FPDataProcessing2SourceFMask = 0x5F200C00, | |
1114 FPDataProcessing2SourceMask = 0xFFE0FC00, | |
1115 FMUL = FPDataProcessing2SourceFixed | 0x00000000, | |
1116 FMUL_s = FMUL, | |
1117 FMUL_d = FMUL | FP64, | |
1118 FDIV = FPDataProcessing2SourceFixed | 0x00001000, | |
1119 FDIV_s = FDIV, | |
1120 FDIV_d = FDIV | FP64, | |
1121 FADD = FPDataProcessing2SourceFixed | 0x00002000, | |
1122 FADD_s = FADD, | |
1123 FADD_d = FADD | FP64, | |
1124 FSUB = FPDataProcessing2SourceFixed | 0x00003000, | |
1125 FSUB_s = FSUB, | |
1126 FSUB_d = FSUB | FP64, | |
1127 FMAX = FPDataProcessing2SourceFixed | 0x00004000, | |
1128 FMAX_s = FMAX, | |
1129 FMAX_d = FMAX | FP64, | |
1130 FMIN = FPDataProcessing2SourceFixed | 0x00005000, | |
1131 FMIN_s = FMIN, | |
1132 FMIN_d = FMIN | FP64, | |
1133 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000, | |
1134 FMAXNM_s = FMAXNM, | |
1135 FMAXNM_d = FMAXNM | FP64, | |
1136 FMINNM = FPDataProcessing2SourceFixed | 0x00007000, | |
1137 FMINNM_s = FMINNM, | |
1138 FMINNM_d = FMINNM | FP64, | |
1139 FNMUL = FPDataProcessing2SourceFixed | 0x00008000, | |
1140 FNMUL_s = FNMUL, | |
1141 FNMUL_d = FNMUL | FP64 | |
1142 }; | |
1143 | |
1144 // Floating point data processing 3 source. | |
1145 enum FPDataProcessing3SourceOp { | |
1146 FPDataProcessing3SourceFixed = 0x1F000000, | |
1147 FPDataProcessing3SourceFMask = 0x5F000000, | |
1148 FPDataProcessing3SourceMask = 0xFFE08000, | |
1149 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000, | |
1150 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000, | |
1151 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000, | |
1152 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000, | |
1153 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000, | |
1154 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000, | |
1155 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000, | |
1156 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000 | |
1157 }; | |
1158 | |
1159 // Conversion between floating point and integer. | |
1160 enum FPIntegerConvertOp { | |
1161 FPIntegerConvertFixed = 0x1E200000, | |
1162 FPIntegerConvertFMask = 0x5F20FC00, | |
1163 FPIntegerConvertMask = 0xFFFFFC00, | |
1164 FCVTNS = FPIntegerConvertFixed | 0x00000000, | |
1165 FCVTNS_ws = FCVTNS, | |
1166 FCVTNS_xs = FCVTNS | SixtyFourBits, | |
1167 FCVTNS_wd = FCVTNS | FP64, | |
1168 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64, | |
1169 FCVTNU = FPIntegerConvertFixed | 0x00010000, | |
1170 FCVTNU_ws = FCVTNU, | |
1171 FCVTNU_xs = FCVTNU | SixtyFourBits, | |
1172 FCVTNU_wd = FCVTNU | FP64, | |
1173 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64, | |
1174 FCVTPS = FPIntegerConvertFixed | 0x00080000, | |
1175 FCVTPS_ws = FCVTPS, | |
1176 FCVTPS_xs = FCVTPS | SixtyFourBits, | |
1177 FCVTPS_wd = FCVTPS | FP64, | |
1178 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64, | |
1179 FCVTPU = FPIntegerConvertFixed | 0x00090000, | |
1180 FCVTPU_ws = FCVTPU, | |
1181 FCVTPU_xs = FCVTPU | SixtyFourBits, | |
1182 FCVTPU_wd = FCVTPU | FP64, | |
1183 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64, | |
1184 FCVTMS = FPIntegerConvertFixed | 0x00100000, | |
1185 FCVTMS_ws = FCVTMS, | |
1186 FCVTMS_xs = FCVTMS | SixtyFourBits, | |
1187 FCVTMS_wd = FCVTMS | FP64, | |
1188 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64, | |
1189 FCVTMU = FPIntegerConvertFixed | 0x00110000, | |
1190 FCVTMU_ws = FCVTMU, | |
1191 FCVTMU_xs = FCVTMU | SixtyFourBits, | |
1192 FCVTMU_wd = FCVTMU | FP64, | |
1193 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64, | |
1194 FCVTZS = FPIntegerConvertFixed | 0x00180000, | |
1195 FCVTZS_ws = FCVTZS, | |
1196 FCVTZS_xs = FCVTZS | SixtyFourBits, | |
1197 FCVTZS_wd = FCVTZS | FP64, | |
1198 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64, | |
1199 FCVTZU = FPIntegerConvertFixed | 0x00190000, | |
1200 FCVTZU_ws = FCVTZU, | |
1201 FCVTZU_xs = FCVTZU | SixtyFourBits, | |
1202 FCVTZU_wd = FCVTZU | FP64, | |
1203 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64, | |
1204 SCVTF = FPIntegerConvertFixed | 0x00020000, | |
1205 SCVTF_sw = SCVTF, | |
1206 SCVTF_sx = SCVTF | SixtyFourBits, | |
1207 SCVTF_dw = SCVTF | FP64, | |
1208 SCVTF_dx = SCVTF | SixtyFourBits | FP64, | |
1209 UCVTF = FPIntegerConvertFixed | 0x00030000, | |
1210 UCVTF_sw = UCVTF, | |
1211 UCVTF_sx = UCVTF | SixtyFourBits, | |
1212 UCVTF_dw = UCVTF | FP64, | |
1213 UCVTF_dx = UCVTF | SixtyFourBits | FP64, | |
1214 FCVTAS = FPIntegerConvertFixed | 0x00040000, | |
1215 FCVTAS_ws = FCVTAS, | |
1216 FCVTAS_xs = FCVTAS | SixtyFourBits, | |
1217 FCVTAS_wd = FCVTAS | FP64, | |
1218 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64, | |
1219 FCVTAU = FPIntegerConvertFixed | 0x00050000, | |
1220 FCVTAU_ws = FCVTAU, | |
1221 FCVTAU_xs = FCVTAU | SixtyFourBits, | |
1222 FCVTAU_wd = FCVTAU | FP64, | |
1223 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64, | |
1224 FMOV_ws = FPIntegerConvertFixed | 0x00060000, | |
1225 FMOV_sw = FPIntegerConvertFixed | 0x00070000, | |
1226 FMOV_xd = FMOV_ws | SixtyFourBits | FP64, | |
1227 FMOV_dx = FMOV_sw | SixtyFourBits | FP64 | |
1228 }; | |
1229 | |
1230 // Conversion between fixed point and floating point. | |
1231 enum FPFixedPointConvertOp { | |
1232 FPFixedPointConvertFixed = 0x1E000000, | |
1233 FPFixedPointConvertFMask = 0x5F200000, | |
1234 FPFixedPointConvertMask = 0xFFFF0000, | |
1235 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000, | |
1236 FCVTZS_ws_fixed = FCVTZS_fixed, | |
1237 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits, | |
1238 FCVTZS_wd_fixed = FCVTZS_fixed | FP64, | |
1239 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64, | |
1240 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000, | |
1241 FCVTZU_ws_fixed = FCVTZU_fixed, | |
1242 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits, | |
1243 FCVTZU_wd_fixed = FCVTZU_fixed | FP64, | |
1244 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64, | |
1245 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000, | |
1246 SCVTF_sw_fixed = SCVTF_fixed, | |
1247 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits, | |
1248 SCVTF_dw_fixed = SCVTF_fixed | FP64, | |
1249 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64, | |
1250 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000, | |
1251 UCVTF_sw_fixed = UCVTF_fixed, | |
1252 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits, | |
1253 UCVTF_dw_fixed = UCVTF_fixed | FP64, | |
1254 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64 | |
1255 }; | |
1256 | |
1257 // Unimplemented and unallocated instructions. These are defined to make fixed | |
1258 // bit assertion easier. | |
1259 enum UnimplementedOp { | |
1260 UnimplementedFixed = 0x00000000, | |
1261 UnimplementedFMask = 0x00000000 | |
1262 }; | |
1263 | |
1264 enum UnallocatedOp { | |
1265 UnallocatedFixed = 0x00000000, | |
1266 UnallocatedFMask = 0x00000000 | |
1267 }; | |
1268 | |
1269 } } // namespace v8::internal | |
1270 | |
1271 #endif // V8_A64_CONSTANTS_A64_H_ | |
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