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Side by Side Diff: src/s390/macro-assembler-s390.cc

Issue 2072963003: Simplify AssemblerPositionsRecorder. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: addressed comment Created 4 years, 6 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <assert.h> // For assert 5 #include <assert.h> // For assert
6 #include <limits.h> // For LONG_MIN, LONG_MAX. 6 #include <limits.h> // For LONG_MIN, LONG_MAX.
7 7
8 #if V8_TARGET_ARCH_S390 8 #if V8_TARGET_ARCH_S390
9 9
10 #include "src/base/bits.h" 10 #include "src/base/bits.h"
(...skipping 52 matching lines...) Expand 10 before | Expand all | Expand 10 after
63 DCHECK(RelocInfo::IsCodeTarget(rmode)); 63 DCHECK(RelocInfo::IsCodeTarget(rmode));
64 jump(code, rmode, cond); 64 jump(code, rmode, cond);
65 } 65 }
66 66
67 int MacroAssembler::CallSize(Register target) { return 2; } // BASR 67 int MacroAssembler::CallSize(Register target) { return 2; } // BASR
68 68
69 void MacroAssembler::Call(Register target) { 69 void MacroAssembler::Call(Register target) {
70 Label start; 70 Label start;
71 bind(&start); 71 bind(&start);
72 72
73 // Statement positions are expected to be recorded when the target
74 // address is loaded.
75 positions_recorder()->WriteRecordedPositions();
76
77 // Branch to target via indirect branch 73 // Branch to target via indirect branch
78 basr(r14, target); 74 basr(r14, target);
79 75
80 DCHECK_EQ(CallSize(target), SizeOfCodeGeneratedSince(&start)); 76 DCHECK_EQ(CallSize(target), SizeOfCodeGeneratedSince(&start));
81 } 77 }
82 78
83 void MacroAssembler::CallJSEntry(Register target) { 79 void MacroAssembler::CallJSEntry(Register target) {
84 DCHECK(target.is(ip)); 80 DCHECK(target.is(ip));
85 Call(target); 81 Call(target);
86 } 82 }
(...skipping 28 matching lines...) Expand all
115 DCHECK(cond == al); 111 DCHECK(cond == al);
116 112
117 #ifdef DEBUG 113 #ifdef DEBUG
118 // Check the expected size before generating code to ensure we assume the same 114 // Check the expected size before generating code to ensure we assume the same
119 // constant pool availability (e.g., whether constant pool is full or not). 115 // constant pool availability (e.g., whether constant pool is full or not).
120 int expected_size = CallSize(target, rmode, cond); 116 int expected_size = CallSize(target, rmode, cond);
121 Label start; 117 Label start;
122 bind(&start); 118 bind(&start);
123 #endif 119 #endif
124 120
125 // Statement positions are expected to be recorded when the target
126 // address is loaded.
127 positions_recorder()->WriteRecordedPositions();
128
129 mov(ip, Operand(reinterpret_cast<intptr_t>(target), rmode)); 121 mov(ip, Operand(reinterpret_cast<intptr_t>(target), rmode));
130 basr(r14, ip); 122 basr(r14, ip);
131 123
132 DCHECK_EQ(expected_size, SizeOfCodeGeneratedSince(&start)); 124 DCHECK_EQ(expected_size, SizeOfCodeGeneratedSince(&start));
133 } 125 }
134 126
135 int MacroAssembler::CallSize(Handle<Code> code, RelocInfo::Mode rmode, 127 int MacroAssembler::CallSize(Handle<Code> code, RelocInfo::Mode rmode,
136 TypeFeedbackId ast_id, Condition cond) { 128 TypeFeedbackId ast_id, Condition cond) {
137 return 6; // BRASL 129 return 6; // BRASL
138 } 130 }
(...skipping 4611 matching lines...) Expand 10 before | Expand all | Expand 10 after
4750 intptr_t value = opnd.immediate(); 4742 intptr_t value = opnd.immediate();
4751 if (is_int16(value)) 4743 if (is_int16(value))
4752 brc(c, opnd); 4744 brc(c, opnd);
4753 else 4745 else
4754 brcl(c, opnd); 4746 brcl(c, opnd);
4755 } 4747 }
4756 4748
4757 // Branch On Count. Decrement R1, and branch if R1 != 0. 4749 // Branch On Count. Decrement R1, and branch if R1 != 0.
4758 void MacroAssembler::BranchOnCount(Register r1, Label* l) { 4750 void MacroAssembler::BranchOnCount(Register r1, Label* l) {
4759 int32_t offset = branch_offset(l); 4751 int32_t offset = branch_offset(l);
4760 positions_recorder()->WriteRecordedPositions();
4761 if (is_int16(offset)) { 4752 if (is_int16(offset)) {
4762 #if V8_TARGET_ARCH_S390X 4753 #if V8_TARGET_ARCH_S390X
4763 brctg(r1, Operand(offset)); 4754 brctg(r1, Operand(offset));
4764 #else 4755 #else
4765 brct(r1, Operand(offset)); 4756 brct(r1, Operand(offset));
4766 #endif 4757 #endif
4767 } else { 4758 } else {
4768 AddP(r1, Operand(-1)); 4759 AddP(r1, Operand(-1));
4769 Branch(ne, Operand(offset)); 4760 Branch(ne, Operand(offset));
4770 } 4761 }
(...skipping 755 matching lines...) Expand 10 before | Expand all | Expand 10 after
5526 } 5517 }
5527 if (mag.shift > 0) ShiftRightArith(result, result, Operand(mag.shift)); 5518 if (mag.shift > 0) ShiftRightArith(result, result, Operand(mag.shift));
5528 ExtractBit(r0, dividend, 31); 5519 ExtractBit(r0, dividend, 31);
5529 AddP(result, r0); 5520 AddP(result, r0);
5530 } 5521 }
5531 5522
5532 } // namespace internal 5523 } // namespace internal
5533 } // namespace v8 5524 } // namespace v8
5534 5525
5535 #endif // V8_TARGET_ARCH_S390 5526 #endif // V8_TARGET_ARCH_S390
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