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Side by Side Diff: src/arm64/assembler-arm64.cc

Issue 2072963003: Simplify AssemblerPositionsRecorder. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: addressed comment Created 4 years, 6 months ago
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1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // 2 //
3 // Redistribution and use in source and binary forms, with or without 3 // Redistribution and use in source and binary forms, with or without
4 // modification, are permitted provided that the following conditions are 4 // modification, are permitted provided that the following conditions are
5 // met: 5 // met:
6 // 6 //
7 // * Redistributions of source code must retain the above copyright 7 // * Redistributions of source code must retain the above copyright
8 // notice, this list of conditions and the following disclaimer. 8 // notice, this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above 9 // * Redistributions in binary form must reproduce the above
10 // copyright notice, this list of conditions and the following 10 // copyright notice, this list of conditions and the following
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964 void Assembler::EndBlockVeneerPool() { 964 void Assembler::EndBlockVeneerPool() {
965 if (--veneer_pool_blocked_nesting_ == 0) { 965 if (--veneer_pool_blocked_nesting_ == 0) {
966 // Check the veneer pool hasn't been blocked for too long. 966 // Check the veneer pool hasn't been blocked for too long.
967 DCHECK(unresolved_branches_.empty() || 967 DCHECK(unresolved_branches_.empty() ||
968 (pc_offset() < unresolved_branches_first_limit())); 968 (pc_offset() < unresolved_branches_first_limit()));
969 } 969 }
970 } 970 }
971 971
972 972
973 void Assembler::br(const Register& xn) { 973 void Assembler::br(const Register& xn) {
974 positions_recorder()->WriteRecordedPositions();
975 DCHECK(xn.Is64Bits()); 974 DCHECK(xn.Is64Bits());
976 Emit(BR | Rn(xn)); 975 Emit(BR | Rn(xn));
977 } 976 }
978 977
979 978
980 void Assembler::blr(const Register& xn) { 979 void Assembler::blr(const Register& xn) {
981 positions_recorder()->WriteRecordedPositions();
982 DCHECK(xn.Is64Bits()); 980 DCHECK(xn.Is64Bits());
983 // The pattern 'blr xzr' is used as a guard to detect when execution falls 981 // The pattern 'blr xzr' is used as a guard to detect when execution falls
984 // through the constant pool. It should not be emitted. 982 // through the constant pool. It should not be emitted.
985 DCHECK(!xn.Is(xzr)); 983 DCHECK(!xn.Is(xzr));
986 Emit(BLR | Rn(xn)); 984 Emit(BLR | Rn(xn));
987 } 985 }
988 986
989 987
990 void Assembler::ret(const Register& xn) { 988 void Assembler::ret(const Register& xn) {
991 positions_recorder()->WriteRecordedPositions();
992 DCHECK(xn.Is64Bits()); 989 DCHECK(xn.Is64Bits());
993 Emit(RET | Rn(xn)); 990 Emit(RET | Rn(xn));
994 } 991 }
995 992
996 993
997 void Assembler::b(int imm26) { 994 void Assembler::b(int imm26) {
998 Emit(B | ImmUncondBranch(imm26)); 995 Emit(B | ImmUncondBranch(imm26));
999 } 996 }
1000 997
1001 998
1002 void Assembler::b(Label* label) { 999 void Assembler::b(Label* label) {
1003 positions_recorder()->WriteRecordedPositions();
1004 b(LinkAndGetInstructionOffsetTo(label)); 1000 b(LinkAndGetInstructionOffsetTo(label));
1005 } 1001 }
1006 1002
1007 1003
1008 void Assembler::b(int imm19, Condition cond) { 1004 void Assembler::b(int imm19, Condition cond) {
1009 Emit(B_cond | ImmCondBranch(imm19) | cond); 1005 Emit(B_cond | ImmCondBranch(imm19) | cond);
1010 } 1006 }
1011 1007
1012 1008
1013 void Assembler::b(Label* label, Condition cond) { 1009 void Assembler::b(Label* label, Condition cond) {
1014 positions_recorder()->WriteRecordedPositions();
1015 b(LinkAndGetInstructionOffsetTo(label), cond); 1010 b(LinkAndGetInstructionOffsetTo(label), cond);
1016 } 1011 }
1017 1012
1018 1013
1019 void Assembler::bl(int imm26) { 1014 void Assembler::bl(int imm26) {
1020 positions_recorder()->WriteRecordedPositions();
1021 Emit(BL | ImmUncondBranch(imm26)); 1015 Emit(BL | ImmUncondBranch(imm26));
1022 } 1016 }
1023 1017
1024 1018
1025 void Assembler::bl(Label* label) { 1019 void Assembler::bl(Label* label) {
1026 positions_recorder()->WriteRecordedPositions();
1027 bl(LinkAndGetInstructionOffsetTo(label)); 1020 bl(LinkAndGetInstructionOffsetTo(label));
1028 } 1021 }
1029 1022
1030 1023
1031 void Assembler::cbz(const Register& rt, 1024 void Assembler::cbz(const Register& rt,
1032 int imm19) { 1025 int imm19) {
1033 positions_recorder()->WriteRecordedPositions();
1034 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt)); 1026 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt));
1035 } 1027 }
1036 1028
1037 1029
1038 void Assembler::cbz(const Register& rt, 1030 void Assembler::cbz(const Register& rt,
1039 Label* label) { 1031 Label* label) {
1040 positions_recorder()->WriteRecordedPositions();
1041 cbz(rt, LinkAndGetInstructionOffsetTo(label)); 1032 cbz(rt, LinkAndGetInstructionOffsetTo(label));
1042 } 1033 }
1043 1034
1044 1035
1045 void Assembler::cbnz(const Register& rt, 1036 void Assembler::cbnz(const Register& rt,
1046 int imm19) { 1037 int imm19) {
1047 positions_recorder()->WriteRecordedPositions();
1048 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt)); 1038 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt));
1049 } 1039 }
1050 1040
1051 1041
1052 void Assembler::cbnz(const Register& rt, 1042 void Assembler::cbnz(const Register& rt,
1053 Label* label) { 1043 Label* label) {
1054 positions_recorder()->WriteRecordedPositions();
1055 cbnz(rt, LinkAndGetInstructionOffsetTo(label)); 1044 cbnz(rt, LinkAndGetInstructionOffsetTo(label));
1056 } 1045 }
1057 1046
1058 1047
1059 void Assembler::tbz(const Register& rt, 1048 void Assembler::tbz(const Register& rt,
1060 unsigned bit_pos, 1049 unsigned bit_pos,
1061 int imm14) { 1050 int imm14) {
1062 positions_recorder()->WriteRecordedPositions();
1063 DCHECK(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits))); 1051 DCHECK(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits)));
1064 Emit(TBZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt)); 1052 Emit(TBZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
1065 } 1053 }
1066 1054
1067 1055
1068 void Assembler::tbz(const Register& rt, 1056 void Assembler::tbz(const Register& rt,
1069 unsigned bit_pos, 1057 unsigned bit_pos,
1070 Label* label) { 1058 Label* label) {
1071 positions_recorder()->WriteRecordedPositions();
1072 tbz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label)); 1059 tbz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label));
1073 } 1060 }
1074 1061
1075 1062
1076 void Assembler::tbnz(const Register& rt, 1063 void Assembler::tbnz(const Register& rt,
1077 unsigned bit_pos, 1064 unsigned bit_pos,
1078 int imm14) { 1065 int imm14) {
1079 positions_recorder()->WriteRecordedPositions();
1080 DCHECK(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits))); 1066 DCHECK(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits)));
1081 Emit(TBNZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt)); 1067 Emit(TBNZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
1082 } 1068 }
1083 1069
1084 1070
1085 void Assembler::tbnz(const Register& rt, 1071 void Assembler::tbnz(const Register& rt,
1086 unsigned bit_pos, 1072 unsigned bit_pos,
1087 Label* label) { 1073 Label* label) {
1088 positions_recorder()->WriteRecordedPositions();
1089 tbnz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label)); 1074 tbnz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label));
1090 } 1075 }
1091 1076
1092 1077
1093 void Assembler::adr(const Register& rd, int imm21) { 1078 void Assembler::adr(const Register& rd, int imm21) {
1094 DCHECK(rd.Is64Bits()); 1079 DCHECK(rd.Is64Bits());
1095 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd)); 1080 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd));
1096 } 1081 }
1097 1082
1098 1083
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3228 movk(scratch, (target_offset >> 32) & 0xFFFF, 32); 3213 movk(scratch, (target_offset >> 32) & 0xFFFF, 32);
3229 DCHECK((target_offset >> 48) == 0); 3214 DCHECK((target_offset >> 48) == 0);
3230 add(rd, rd, scratch); 3215 add(rd, rd, scratch);
3231 } 3216 }
3232 3217
3233 3218
3234 } // namespace internal 3219 } // namespace internal
3235 } // namespace v8 3220 } // namespace v8
3236 3221
3237 #endif // V8_TARGET_ARCH_ARM64 3222 #endif // V8_TARGET_ARCH_ARM64
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