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| 1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
| 2 // | 2 // |
| 3 // Redistribution and use in source and binary forms, with or without | 3 // Redistribution and use in source and binary forms, with or without |
| 4 // modification, are permitted provided that the following conditions are | 4 // modification, are permitted provided that the following conditions are |
| 5 // met: | 5 // met: |
| 6 // | 6 // |
| 7 // * Redistributions of source code must retain the above copyright | 7 // * Redistributions of source code must retain the above copyright |
| 8 // notice, this list of conditions and the following disclaimer. | 8 // notice, this list of conditions and the following disclaimer. |
| 9 // * Redistributions in binary form must reproduce the above | 9 // * Redistributions in binary form must reproduce the above |
| 10 // copyright notice, this list of conditions and the following | 10 // copyright notice, this list of conditions and the following |
| (...skipping 980 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 991 void Assembler::EndBlockVeneerPool() { | 991 void Assembler::EndBlockVeneerPool() { |
| 992 if (--veneer_pool_blocked_nesting_ == 0) { | 992 if (--veneer_pool_blocked_nesting_ == 0) { |
| 993 // Check the veneer pool hasn't been blocked for too long. | 993 // Check the veneer pool hasn't been blocked for too long. |
| 994 DCHECK(unresolved_branches_.empty() || | 994 DCHECK(unresolved_branches_.empty() || |
| 995 (pc_offset() < unresolved_branches_first_limit())); | 995 (pc_offset() < unresolved_branches_first_limit())); |
| 996 } | 996 } |
| 997 } | 997 } |
| 998 | 998 |
| 999 | 999 |
| 1000 void Assembler::br(const Register& xn) { | 1000 void Assembler::br(const Register& xn) { |
| 1001 positions_recorder()->WriteRecordedPositions(); | |
| 1002 DCHECK(xn.Is64Bits()); | 1001 DCHECK(xn.Is64Bits()); |
| 1003 Emit(BR | Rn(xn)); | 1002 Emit(BR | Rn(xn)); |
| 1004 } | 1003 } |
| 1005 | 1004 |
| 1006 | 1005 |
| 1007 void Assembler::blr(const Register& xn) { | 1006 void Assembler::blr(const Register& xn) { |
| 1008 positions_recorder()->WriteRecordedPositions(); | |
| 1009 DCHECK(xn.Is64Bits()); | 1007 DCHECK(xn.Is64Bits()); |
| 1010 // The pattern 'blr xzr' is used as a guard to detect when execution falls | 1008 // The pattern 'blr xzr' is used as a guard to detect when execution falls |
| 1011 // through the constant pool. It should not be emitted. | 1009 // through the constant pool. It should not be emitted. |
| 1012 DCHECK(!xn.Is(xzr)); | 1010 DCHECK(!xn.Is(xzr)); |
| 1013 Emit(BLR | Rn(xn)); | 1011 Emit(BLR | Rn(xn)); |
| 1014 } | 1012 } |
| 1015 | 1013 |
| 1016 | 1014 |
| 1017 void Assembler::ret(const Register& xn) { | 1015 void Assembler::ret(const Register& xn) { |
| 1018 positions_recorder()->WriteRecordedPositions(); | |
| 1019 DCHECK(xn.Is64Bits()); | 1016 DCHECK(xn.Is64Bits()); |
| 1020 Emit(RET | Rn(xn)); | 1017 Emit(RET | Rn(xn)); |
| 1021 } | 1018 } |
| 1022 | 1019 |
| 1023 | 1020 |
| 1024 void Assembler::b(int imm26) { | 1021 void Assembler::b(int imm26) { |
| 1025 Emit(B | ImmUncondBranch(imm26)); | 1022 Emit(B | ImmUncondBranch(imm26)); |
| 1026 } | 1023 } |
| 1027 | 1024 |
| 1028 | 1025 |
| 1029 void Assembler::b(Label* label) { | 1026 void Assembler::b(Label* label) { |
| 1030 positions_recorder()->WriteRecordedPositions(); | |
| 1031 b(LinkAndGetInstructionOffsetTo(label)); | 1027 b(LinkAndGetInstructionOffsetTo(label)); |
| 1032 } | 1028 } |
| 1033 | 1029 |
| 1034 | 1030 |
| 1035 void Assembler::b(int imm19, Condition cond) { | 1031 void Assembler::b(int imm19, Condition cond) { |
| 1036 Emit(B_cond | ImmCondBranch(imm19) | cond); | 1032 Emit(B_cond | ImmCondBranch(imm19) | cond); |
| 1037 } | 1033 } |
| 1038 | 1034 |
| 1039 | 1035 |
| 1040 void Assembler::b(Label* label, Condition cond) { | 1036 void Assembler::b(Label* label, Condition cond) { |
| 1041 positions_recorder()->WriteRecordedPositions(); | |
| 1042 b(LinkAndGetInstructionOffsetTo(label), cond); | 1037 b(LinkAndGetInstructionOffsetTo(label), cond); |
| 1043 } | 1038 } |
| 1044 | 1039 |
| 1045 | 1040 |
| 1046 void Assembler::bl(int imm26) { | 1041 void Assembler::bl(int imm26) { |
| 1047 positions_recorder()->WriteRecordedPositions(); | |
| 1048 Emit(BL | ImmUncondBranch(imm26)); | 1042 Emit(BL | ImmUncondBranch(imm26)); |
| 1049 } | 1043 } |
| 1050 | 1044 |
| 1051 | 1045 |
| 1052 void Assembler::bl(Label* label) { | 1046 void Assembler::bl(Label* label) { |
| 1053 positions_recorder()->WriteRecordedPositions(); | |
| 1054 bl(LinkAndGetInstructionOffsetTo(label)); | 1047 bl(LinkAndGetInstructionOffsetTo(label)); |
| 1055 } | 1048 } |
| 1056 | 1049 |
| 1057 | 1050 |
| 1058 void Assembler::cbz(const Register& rt, | 1051 void Assembler::cbz(const Register& rt, |
| 1059 int imm19) { | 1052 int imm19) { |
| 1060 positions_recorder()->WriteRecordedPositions(); | |
| 1061 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt)); | 1053 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt)); |
| 1062 } | 1054 } |
| 1063 | 1055 |
| 1064 | 1056 |
| 1065 void Assembler::cbz(const Register& rt, | 1057 void Assembler::cbz(const Register& rt, |
| 1066 Label* label) { | 1058 Label* label) { |
| 1067 positions_recorder()->WriteRecordedPositions(); | |
| 1068 cbz(rt, LinkAndGetInstructionOffsetTo(label)); | 1059 cbz(rt, LinkAndGetInstructionOffsetTo(label)); |
| 1069 } | 1060 } |
| 1070 | 1061 |
| 1071 | 1062 |
| 1072 void Assembler::cbnz(const Register& rt, | 1063 void Assembler::cbnz(const Register& rt, |
| 1073 int imm19) { | 1064 int imm19) { |
| 1074 positions_recorder()->WriteRecordedPositions(); | |
| 1075 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt)); | 1065 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt)); |
| 1076 } | 1066 } |
| 1077 | 1067 |
| 1078 | 1068 |
| 1079 void Assembler::cbnz(const Register& rt, | 1069 void Assembler::cbnz(const Register& rt, |
| 1080 Label* label) { | 1070 Label* label) { |
| 1081 positions_recorder()->WriteRecordedPositions(); | |
| 1082 cbnz(rt, LinkAndGetInstructionOffsetTo(label)); | 1071 cbnz(rt, LinkAndGetInstructionOffsetTo(label)); |
| 1083 } | 1072 } |
| 1084 | 1073 |
| 1085 | 1074 |
| 1086 void Assembler::tbz(const Register& rt, | 1075 void Assembler::tbz(const Register& rt, |
| 1087 unsigned bit_pos, | 1076 unsigned bit_pos, |
| 1088 int imm14) { | 1077 int imm14) { |
| 1089 positions_recorder()->WriteRecordedPositions(); | |
| 1090 DCHECK(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits))); | 1078 DCHECK(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits))); |
| 1091 Emit(TBZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt)); | 1079 Emit(TBZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt)); |
| 1092 } | 1080 } |
| 1093 | 1081 |
| 1094 | 1082 |
| 1095 void Assembler::tbz(const Register& rt, | 1083 void Assembler::tbz(const Register& rt, |
| 1096 unsigned bit_pos, | 1084 unsigned bit_pos, |
| 1097 Label* label) { | 1085 Label* label) { |
| 1098 positions_recorder()->WriteRecordedPositions(); | |
| 1099 tbz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label)); | 1086 tbz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label)); |
| 1100 } | 1087 } |
| 1101 | 1088 |
| 1102 | 1089 |
| 1103 void Assembler::tbnz(const Register& rt, | 1090 void Assembler::tbnz(const Register& rt, |
| 1104 unsigned bit_pos, | 1091 unsigned bit_pos, |
| 1105 int imm14) { | 1092 int imm14) { |
| 1106 positions_recorder()->WriteRecordedPositions(); | |
| 1107 DCHECK(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits))); | 1093 DCHECK(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits))); |
| 1108 Emit(TBNZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt)); | 1094 Emit(TBNZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt)); |
| 1109 } | 1095 } |
| 1110 | 1096 |
| 1111 | 1097 |
| 1112 void Assembler::tbnz(const Register& rt, | 1098 void Assembler::tbnz(const Register& rt, |
| 1113 unsigned bit_pos, | 1099 unsigned bit_pos, |
| 1114 Label* label) { | 1100 Label* label) { |
| 1115 positions_recorder()->WriteRecordedPositions(); | |
| 1116 tbnz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label)); | 1101 tbnz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label)); |
| 1117 } | 1102 } |
| 1118 | 1103 |
| 1119 | 1104 |
| 1120 void Assembler::adr(const Register& rd, int imm21) { | 1105 void Assembler::adr(const Register& rd, int imm21) { |
| 1121 DCHECK(rd.Is64Bits()); | 1106 DCHECK(rd.Is64Bits()); |
| 1122 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd)); | 1107 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd)); |
| 1123 } | 1108 } |
| 1124 | 1109 |
| 1125 | 1110 |
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| 3255 movk(scratch, (target_offset >> 32) & 0xFFFF, 32); | 3240 movk(scratch, (target_offset >> 32) & 0xFFFF, 32); |
| 3256 DCHECK((target_offset >> 48) == 0); | 3241 DCHECK((target_offset >> 48) == 0); |
| 3257 add(rd, rd, scratch); | 3242 add(rd, rd, scratch); |
| 3258 } | 3243 } |
| 3259 | 3244 |
| 3260 | 3245 |
| 3261 } // namespace internal | 3246 } // namespace internal |
| 3262 } // namespace v8 | 3247 } // namespace v8 |
| 3263 | 3248 |
| 3264 #endif // V8_TARGET_ARCH_ARM64 | 3249 #endif // V8_TARGET_ARCH_ARM64 |
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